Performance enhancement in Ge pMOSFETs with orientation fabricated with a Si-compatible process flow

✍ Scribed by S. Dutta Gupta; J. Mitard; G. Eneman; B. De Jaeger; M. Meuris; M.M. Heyns

• Book ID: 104052658
• Publisher: Elsevier Science
• Year: 2010
• Tongue: English
• Weight: 911 KB
• Volume: 87
• Category: Article
• ISSN: 0167-9317
• DOI: 10.1016/j.mee.2010.01.010

✦ Synopsis

The electrical characterization of Ge pMOSFETs having <1 1 0> and <1 0 0> orientations with gate lengths of 3 lm have been demonstrated with a Si-compatible process flow. Employment of <1 0 0> orientation in Ge pMOSFETs without incorporation of strain provided $10% enhancement in effective hole mobility and drive current when compared to <1 1 0> oriented regular transistors. In this fabrication technology, the effective hole mobility improves from 190 cm 2 /V s for <1 1 0> devices to 210 cm 2 /V s for the <1 0 0> oriented Ge devices at room temperature, which is $2 times the hole mobility of Si pFET devices. This study also presents first time investigation of post metallization anneal (PMA) at 350 °C in H 2 ambient for <1 0 0> Ge pMOSFETs. The overall performance of the devices has been enhanced by 15% after performing PMA. It is likely attributed to a strong decrease of D it , improving the transistor performance. These results indicate that the <1 0 0> Ge pMOSFETs could be a viable candidate for future low voltage high speed CMOS applications.