Partial element equivalent circuit (PEEC) models for on-chip passives and interconnects

✍ Scribed by Menno E. Verbeek

• Publisher: John Wiley and Sons
• Year: 2004
• Tongue: English
• Weight: 296 KB
• Volume: 17
• Category: Article
• ISSN: 0894-3370
• DOI: 10.1002/jnm.524

✦ Synopsis

Abstract

The accurate simulation of the electromagnetic behaviour of interconnects and on‐chip inductors is becoming more and more important for chip designs. For this purpose, we investigate the use of the electric field integral equation, which can be used to construct a full‐wave electromagnetic model. To facilitate the combined analysis of the chip's circuit and the electromagnetic behaviour, the electromagnetic model can be formulated as an equivalent circuit. We have conducted some simple experiments to see the method at work and to obtain an idea of the frequencies for which retardation effects are important. Copyright © 2004 John Wiley & Sons, Ltd.