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๐Ÿ“

Parasitic-Aware Optimization of CMOS RF Circuits

โœ Scribed by Allsoot, Choi, Park


Publisher
Year
2002
Tongue
English
Leaves
181
Category
Library

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โœฆ Table of Contents


Cover......Page 1
Dedication......Page 6
Contents......Page 8
Contributing Authors......Page 14
Preface......Page 16
PART I: BACKGROUND ON PARASITICAWARE OPTIMIZATION......Page 20
1. INTRODUCTION......Page 22
2. OVERVIEW OF WIRELESS TRANSCEIVERS......Page 24
REFERENCES......Page 26
1.1 Background on monolithic inductors......Page 28
1.2 Monolithic inductor realizations......Page 29
1.3 Monolithic inductor models......Page 30
1.4 Expressions for the lumped inductor model......Page 32
1.6 Monolithic 3- D structures......Page 37
1.5 Monolithic transformers......Page 34
1.7 Parasitic- aware inductor model......Page 39
2.1 Diode varactor......Page 43
2.2 Inversion- mode MOS varactors......Page 44
2.3 Accumulation- mode MOSFET......Page 49
3.1 MOS Transistor High frequency model......Page 50
3.2 Noise model of MOS transistor......Page 53
REFERENCES......Page 55
PARASITIC- AWARE OPTIMIZATION......Page 58
1. GRADIENT DECENT OPTIMIZATION......Page 59
2. SIMULATED ANNEALING......Page 60
3.1 Tunneling process......Page 63
3.2 Local Optimization Algorithm......Page 66
3.3 Adaptive Temp Coefficient Determination......Page 68
3.4 Comparison between SA and ASAT......Page 69
4. GENETIC ALGORITHM ( GA)......Page 71
5.1 Particle swarm optimization algorithm theory......Page 74
5.2 Optimization procedure......Page 78
5.3 Optimization parameters......Page 79
6. POST PVT VARIATION OPTIMIZATION......Page 81
REFERENCES......Page 83
PART II: OPTIMIZATION OF CMOS RF CIRCUITS......Page 84
1.1.1 Thermal noise......Page 86
1.1.2 Noise figure......Page 88
1.2.1 1dB gain compression point......Page 89
1.2.2 Two- tone test ( IIP2 and IIP3)......Page 91
2. DESIGN OF LOW NOISE AMPLIFIER......Page 95
3.1 Calculating gate induced noise in SPICE......Page 99
3.2 Calculating Noise figure in SPICE......Page 100
3.3 Saving optimization time......Page 101
3.6 Optimization Simulation Result......Page 103
REFERENCES......Page 105
1. MIXER......Page 108
2. SINGLE BALANCED MIXER......Page 109
2.1 Conversion gain......Page 110
2.2.1 IIP3......Page 111
2.2.2 Calculating IIP3 and conversion power gain......Page 112
2.3.1 DSB and SSB......Page 114
2.4 LO leakage......Page 115
3. DOUBLE BALANCED MIXER......Page 116
4. DESIGN OF MIXERS......Page 117
5.1 Cost function......Page 118
5.3 Optimization simulation results......Page 119
REFERENCES......Page 123
OPTIMIZATION OF CMOS OSCILLATORS......Page 124
1. CMOS OSCILLATORS......Page 125
2.1 Effects of phase noise......Page 128
2.2 Leeson phase noise model......Page 130
2.3 Hajimiri phase noise model......Page 131
3. DESIGN OF VCO......Page 132
4. OPTIMIZATION OF CMOS VCO......Page 134
4.1 Optimization of VCO......Page 135
4.2 Optimization results......Page 136
REFERENCES......Page 139
1. RF POWER AMPLIFIERS......Page 142
1.1.1 Class- A Power Amplifier......Page 143
1.1.2 Class- B Amplifier......Page 145
1.1.3 Class- C Amplifier and Class- AB Amplifier......Page 146
1.2 Nonlinear power amplifiers: Class- F and Class- E......Page 150
1.2.1 Class- F PA......Page 151
1.2.2 Class- E PA......Page 153
3. OPTIMIZATION OF POWER AMPLIFIER......Page 156
4. POST PVT OPTIMIZATION......Page 160
REFERENCES......Page 163
1.1 Distributed amplification theory......Page 164
1.2 CMOS distributed amplifier......Page 167
1.3 Effects of loss in CMOS distributed amplifiers......Page 168
2. DESIGN OF CMOS ULTRA- WIDEBAND AMPLIFIER......Page 171
3. OPTIMIZATION OF CMOS ULTRA- WIDEBAND AMPLIFIER......Page 174
3.2 Optimization results......Page 175
REFERENCES......Page 177
Index......Page 180


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