𝔖 Bobbio Scriptorium

✦ LIBER ✦

Parametric formulation of CMOS latch-up as a function of chip layout parameters

✍ Scribed by Lohia, R.; Ali, A.

Book ID: 119774007
Publisher: IEEE
Year: 1988
Tongue: English
Weight: 475 KB
Volume: 23
Category: Article
ISSN: 0018-9200
DOI: 10.1109/4.285

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Module frequency estimation and noise bu

Module frequency estimation and noise budget limitations/trade-offs in multichip modules as a function of CMOS chips integration

✍ Senthinathan, R.; Prince, J.L.; Cangellaris, A.C. 📂 Article 📅 1993 🏛 IEEE 🌐 English ⚖ 606 KB

Module frequency estimation and noise bu

Module frequency estimation and noise budget limitations/trade-offs in multichip modules as a function of CMOS chips integration : Ramesh Senthinathan. et al. IEEE Transactions on Components, Hybrids and Manufacturing Technology, 16(5), 478 (August 1993)

📂 Article 📅 1994 🏛 Elsevier Science 🌐 English ⚖ 217 KB