Parallel testing of parametric faults in a three-dimensional dynamic random-access memory: P Mazumder (Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA) IEEE J. Solid State Circuits (USA), vol. 23, no. 4, pp. 933–941 (Aug. 1988)
- Publisher
- Elsevier Science
- Year
- 1988
- Tongue
- English
- Weight
- 99 KB
- Volume
- 19
- Category
- Article
- ISSN
- 0026-2692
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✦ Synopsis
A testable design of dynamic random-access memory (DRAM) architecture which allows one to access multiple cells in a word line simultaneously is presented. The technique utilises the two-dimensional (2-D) organisation of the DRAM and the resulting speedup of the conventional algorithm is considerable. The failure mechanism in the three-dimensional (3-D) DRAM with trench-type capacitor is specifically investigated. As opposed to the earlier approaches for testing parametric faults that used sliding diagonaltype tests with O(n 3/2) complexity, the algorithms discussed here are different and have O(v/n/p) complexity, wherep is the number ofsubarrays within the DRAM chip. These algorithms can be applied externally from the chip and also they can be easily generated for built-in self-test applications. (12 refs.