✦ LIBER ✦

Parallel implementation of a 4×4-bit multiplier using a modified Booth's algorithm

✍ Scribed by Shanbhag, N.R.; Juneja, P.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

A fast parallel multiplier-accumulator u

✍ Elguibaly, F. 📂 Article 📅 2000 🏛 IEEE 🌐 English ⚖ 256 KB

A 280-ps Josephson 4-bitx4-bit parallel

✍ Sone, J.; Tsai, J.; Abe, H. 📂 Article 📅 1985 🏛 IEEE 🌐 English ⚖ 939 KB

A New VLSI Architecture of Parallel Mult

✍ Young-Ho Seo; Dong-Wook Kim 📂 Article 📅 2010 🏛 IEEE 🌐 English ⚖ 737 KB

High-density 16/8/4-bit configurable mul

✍ Bermak, A.; Martinez, D.; Noullet, J.-L. 📂 Article 📅 1997 🏛 The Institution of Electrical Engineers 🌐 English ⚖ 778 KB

A parallel implementation of a modified

✍ Al-Bakkar, A. G. ;Ipson, S. S. ;Porter, G. J. ;Gleed, D. G. 📂 Article 📅 1997 🏛 Springer 🌐 English ⚖ 889 KB

Implementation of a 2nd-order digital fi

✍ Allen, P.J.; Holt, A.G.J. 📂 Article 📅 1981 🏛 The Institution of Electrical Engineers ⚖ 605 KB