Cover
Half Title
Title Page
Copyright Page
Contents
Preface
Author Biography
Chapter 1: Introduction
1.1. Background
1.2. Architectures of IEOSNS
1.2.1. Architecture of IEOSNS
1.2.2. Multi-Layer Satellite Networks
1.2.3. Performance of Satellite Constellation
1.2.4. Event-Driven Observation
1.2.5. End-User Operation
1.3. Characteristics of IEOSNS
1.4. Key Technologies for IEOSNS
1.4.1. Intelligent and Smart Sensors and Detectors for Data Collection
1.4.2. High Data Rate Transmission and High-Speed Network Communication
1.4.3. On-Board Data Processing Capabilities
1.5. Typical Systems of On-Board Image Data Processing
1.5.1. Naval Earth Map Observer (NEMO)
1.5.2. BIRD Mission (Fire Monitoring)
1.5.3. PROBA On-Board Data Processing
1.5.4. SpaceCube 2.0
1.5.5. ร-Sat System for Space Mesh
1.5.6. Satellite On-Board Processing (OBP) System
1.6. Conclusion
References
Chapter 2: On-Board Processing for Remotely Sensed Images
2.1. Introduction
2.2. Architecture of On-Board Image Processing
2.3. Topics of On-Board Data Processing
2.3.1. Low-Level On-Board Data Processing
2.3.2. Middle-Level On-Board Data Processing
2.3.3. High-Level On-Board Data Processing
2.4. Challenges of On-Board Data Processing
2.5. Introduction to FPGA
2.5.1. FPGA-Based Design and Implementation for ISE Software
2.5.2. FPGA Development Method Based on System Generator
2.6. Introduction to Reconfigurable Computing Technology
2.7. Conclusion
References
Chapter 3: On-Board Detection and On-Board Matching of Feature Points
3.1. Introduction
3.2. Feature Detector and Descriptor Algorithm
3.2.1. PC-Based Surf Feature Detector and Algorithm
3.2.1.1. Surf Detector
3.2.1.2. BRIEF Descriptor
3.2.1.3. Hamming Distance Matching
3.2.2. FPGA-Based Detection and Matching Algorithm
3.2.2.1. Modification of Integral Image
3.2.2.2. Modification of Hessian Matrix Responses
3.3. FPGA-Based Implementation
3.3.1. The Architecture of FPGA-Based Detection
3.3.2. Implementation of DDR3 Write-Read Control
3.3.3. FPGA-Based Implementation of Integral Image
3.3.4. FPGA Implementation of Hessian Matrix Responses
3.3.5. FPGA-Based Implementation of 3D Non-Maximal Suppression
3.3.6. FPGA-Based Implementation of BRIEF Descriptor
3.3.7. FPGA-Based Implementation of Matching
3.4. Verifications and Analysis
3.4.1. Hardware Environment and Data Set
3.4.2. Verifications and Results
3.4.3. Performance Evaluation
3.4.3.1. Accuracy Analysis
3.4.3.2. Comparison for Computational Speed
3.4.3.3. FPGA Resources Utilization Analysis
3.4.4. Discussion
3.5. Conclusions
References
Chapter 4: On-Board Detection of Ground Control Points
4.1. Introduction
4.2. Feature Detector and Descriptor
4.2.1. SURF Feature Detector
4.2.1.1. Integral Image
4.2.1.2. Extraction of Feature Points
4.2.1.3. Non-Maximum Suppression
4.2.2. BRIEF Descriptor
4.2.3. Hamming Distance Matching
4.3. Optimization Of Surf Detector
4.3.1. Word Length Reduction (WLR)
4.3.2. Parallel Computation for Integral Image
4.3.3. Shift and Subtraction (SAS)
4.3.4. Sliding Window
4.3.5. Parallel Multi-Scale-Space Hessian Determinant
4.4. Hardware Implementation
4.4.1. Architecture of Hardware Implementation
4.4.2. Integral Image Generator (IIG)
4.4.3. SURF Detector Implementation
4.4.3.1. Fast-Hessian Responses Implementation
4.4.3.2. Non-Maximal Suppression Implementation
4.4.4. Implementation for BRIEF Descriptor
4.4.5. Implementation for BRIEF Matching
4.5. Verification and Discussion
4.5.1. Hardware Environment and Data Set
4.5.2. Interest Points Extraction
4.5.3. Error Analysis
4.5.4. Performance Analysis of FPGA
4.5.4.1. FPGA Resources Utilization Analysis
4.5.4.2. Computational Speed Comparison
4.6. Conclusions
References
Chapter 5: On-Board Geometric Calibration for Frame Camera
5.1. Introduction
5.2. The Mathematical Model of Geometric Calibration for Frame Camera
5.3. FPGA-Based Design Structure for On-Board Geometric Calibration
5.3.1. Implementation of Gateway in Module
5.3.2. Implementation of Parameter Calculation Module
5.3.3. Parallel Computation of Matrix Multiplication
5.3.4. FPGA-Based Implementation of On-Board Calibration
5.3.4.1. The Hardware Implementation for Solution of Matrix Inverse
5.3.4.2. Hardware Implementation for Inverse Matrix Using Block LU Decomposition
5.4. Simulation and Verification
5.4.1. Experimental Data
5.4.2. Verification and Hardware Resource Utilization Analysis of Primary Calculation
5.4.3. Implementation and Verification of Iterative Computing System
5.5. Conclusions
References
Chapter 6: On-Board Geometric Calibration for Linear Array CCD Sensor
6.1. Introduction
6.2. Relevant Efforts
6.3. Geometric Calibration Model for Linear Array CCD Sensor
6.3.1. Brief Overview of Geometric Calibration Model
6.3.2. FPGA-Based Implementation of Geometric Calibration
6.3.2.1. The Hardware Architecture
6.3.2.2. FPGA Computation for Matrixes RGR, lt and At
6.3.2.3. FPGA-Based Computation for ATA and ATL
6.3.2.4. FPGA-Based Computation for B1
6.4. Verifications and Performance Analysis
6.4.1. Test Area and Data
6.4.2. Hardware Environment
6.4.3. Determination of the Data Width of Floating-Point
6.4.3.1. Relationship between the Data Width and the Accuracy
6.4.3.2. Relationship between the Data Width and the Consumption of FPGA Resources
6.4.3.3. Relationship between the Data Width and the Computational Time
6.4.4. Analysis of the Optimum Number of GCPs for On-Board Calibration
6.4.4.1. Relationship between the Number of GCPs and the Accuracy
6.4.4.2. Relationship between the Number of GCPs and the Consumption of FPGA Resources
6.4.4.3. Relationship between the Number of GCPs and the Computational Time
6.4.5. Accuracy Comparison between FPGA-Based and Inflight-Based Computation
6.5. Conclusions
References
Chapter 7: On-Board Georeferencing Using Optimized Second-Order Polynomial Equation
7.1. Introduction
7.2. Optimization for On-Board Georeferencing
7.2.1. A Brief Review of Georeferencing Algorithm
7.2.1.1. Traditional Second-Order Polynomial Equations
7.2.1.2. Coordinate Transformation
7.2.1.3. Resampling Using Bilinear Interpolation
7.2.2. Optimized Georeferencing Algorithm
7.2.2.1. Optimized Second-Order Polynomial Model
7.2.2.2. Optimized Bilinear Interpolation
7.3. FPGA-Based Implementation of the Georeferencing
7.3.1. FPGA-Based Solution of the Second-Order Polynomial Equation
7.3.1.1. Calculation of Matrix ATA
7.3.1.2. LU Decomposition of the Matrix ATA
7.3.1.3. FPGA-Based Implantation of the Matrix (ATA)-1
7.3.1.4. FPGA-Based Implementation of a and b Matrices
7.3.2. FPGA-Based Implementation of Coordinate Transformation and Bilinear Interpolation
7.4. Verifications and Performance Analysis
7.4.1. The Software and Hardware Environment
7.4.2. Remotely Sensed Image Data
7.4.3. Processing Performance
7.4.3.1. Error Analysis
7.4.3.2. Gray Value Comparison
7.4.3.3. Resource Occupation Analysis
7.4.3.4. Processing Speed Comparison
7.4.3.5. Power Consumption
7.5. Conclusions
References
Chapter 8: On-Board Image Ortho-Rectification Using Collinearity
8.1. Introduction
8.2. Ortho-Rectification Using FPGA
8.2.1. A Brief Review of the Ortho-Rectification Algorithm
8.2.2. FPGA-Based Implementation for Ortho-Rectification
8.2.2.1. FPGA-Based Implementation for a Two-Row Buffer
8.2.2.2. FPGA-Based Implementation for Coordinate Transformation
8.2.2.3. FPGA-Based Implementation for Bilinear Interpolation
8.3. Experiment
8.3.1. The Software and Hardware Environment
8.3.2. Data Sets
8.4. Discussion
8.4.1. Visual Check
8.4.2. Error Analysis
8.4.3. Processing Speed Comparison
8.4.4. Resource Consumption
8.5. Conclusions
References
Chapter 9: On-Board Image Ortho-Rectification Using RPC Model
9.1. Introduction
9.2. RPC-Based Ortho-Rectification Model Using FPGA Chip
9.2.1. The Improvement of RPC Algorithm with Considering On-Board implementation
9.2.2. Parallel Computation of Ortho-Rectification Using FPGA
9.2.2.1. Read Parameter Module
9.2.2.2. Coordinate Transformation Module
9.2.2.3. Interpolation Module
9.3. Validations
9.3.1. Software and Hardware Environment
9.3.2. Dataset
9.4. Discussions
9.4.1. Error Analysis
9.4.2. Comparison Analysis for Processing Speed
9.4.3. Resource Consumption
9.5. Conclusions
References
Chapter 10: On-Board Flood Change Detection Using SAR Images
10.1. Introduction
10.2. The Proposed Change Detection Method
10.2.1. Log-Ratio
10.2.2. Wavelet Decomposition and Fusion
10.2.3. CFAR Thresholding
10.3. FPGA-Based Hardware Architecture
10.3.1. Implementation of Image Composition (Log-Ratio)
10.3.2. Implementation of Wavelet Decomposition
10.4. Experiment and Discussion
10.4.1. Hardware Environment
10.4.2. Experimental Results
10.5. Conclusion
References
Index