Offset Reduction Techniques in High-Spee
β Pedro M. Figueiredo, JoΓ£o C. Vital
π Library
π
2009
π Springer
π English
β¦ LIBER β¦
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Offset Reduction Techniques in High-Speed Analog-to-Digital Converters: Analysis, Design and Tradeoffs
β Scribed by Pedro M. Figueiredo, JoΓ£o C. Vital
- Publisher
- Springer
- Year
- 2009
- Tongue
- English
- Leaves
- 395
- Series
- Analog Circuits and Signal Processing
- Edition
- 1
- Category
- Library
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β¦ Synopsis
Offset Reduction Techniques in High-Speed Analog-to-Digital ConvertersΒ analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.
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