Narrow distribution of threshold Voltage in 4-Mbit MONOS memory-cell array with F-N channel write and direct/F-N tunneling erase operation as a single transistor structure

✍ Scribed by Nakamura, A.; Moriya, H.; Terano, T.; Kosaka, H.; Hashiguchi, A.; Nomoto, K.; Fujiwara, I.; Kobayashi, T.; Oda, T.

• Book ID: 114617435
• Publisher: IEEE
• Year: 2004
• Tongue: English
• Weight: 474 KB
• Volume: 51
• Category: Article
• ISSN: 0018-9383
• DOI: 10.1109/ted.2004.827369