Multiprocessor Systems on Chip: Design Space Exploration

✍ Scribed by Kempf, Torsten;Ascheid, Gerd;Leupers, Rainer

• Publisher: Springer New York
• Year: 2011
• Tongue: English
• Leaves: 200
• Edition: 1., st edition
• Category: Library

✦ Synopsis

This book gives a comprehensive introduction to the design challenges of MPSoC platforms, focusing on early design space exploration. It defines an iterative methodology to increase the abstraction level so that evaluation of design decisions can be performed earlier in the design process. These techniques enable exploration on the system level before undertaking time- and cost-intensive development.

✦ Table of Contents

Cover......Page 1
C.3 VPU IP Component and Platform Modeling......Page 5
Summary of Task Level Analysis......Page 7
Combination of Algorithms......Page 10
Index......Page 15
A.3 Dependency Delays......Page 4
Multiprocessor Systems on Chip......Page 2
C.2 Task Graph Assembly and Analysis......Page 3
Preface......Page 6
Step 1 (Analytical Model): Initial Setup......Page 13
6.2 Analysis Algorithm......Page 14
List of Tables......Page 16
Step 7 (Analytical Model): Adding a Viterbi CoProcessor......Page 18
1.1 Organization of the Book......Page 20
2.1.1 Wireless Communication Domain......Page 23
Contents......Page 8
Representative Communication Algorithm......Page 9
8.2.3 Exploration......Page 12
Chapter 1 Introduction......Page 17
List of Figures......Page 11
Step 8 (Analytical Model): Tightly Coupled Viterbi CoProcessor......Page 19
7.4.4 Middleware Layer......Page 25
2.1.4 Application Impact on Design Methodology......Page 27
2.2 Hardware Platforms and Components......Page 28
2.2.1 Processing Elements......Page 31
2.2.2 Communication Architectures and Memory Subsystems......Page 34
2.2.3 Hardware Architecture Impact on Design Methodology......Page 35
Chapter 3 Principles of Design Space Exploration......Page 38
Configuration and Initialization......Page 40
3.1.1 Simulation-Based Approaches......Page 41
8.3 Summary of the Case Study......Page 21
Chapter 2 Systems for Wireless Communication......Page 22
2.1.2 Multimedia Applications......Page 24
2.1.3 General Purpose and Other Applications......Page 26
2.3 Summary......Page 36
3.1 Evaluation of a Single Design Point......Page 39
3.1.2 Analytical Approaches......Page 53
3.1.4 Summary of Approaches......Page 55
3.2 Exploring the Design Space......Page 57
3.2.1 Summary of Exploration Approaches......Page 60
4.1 Simulation-Based Approaches......Page 63
4.2 Analytical Approaches......Page 65
4.3 Joint Analytical and Simulation-Based Approaches......Page 67
5.1 Iterative Design Process......Page 69
5.2 Analytical Implementation Model......Page 72
5.3 Abstract Simulation Implementation Model......Page 75
5.4 ISS-Based Implementation Model......Page 78
6.1 Design Space Exploration as a Mathematical Problem......Page 80
6.1.1 Problem Statement and Elementary Definitions......Page 82
6.1.2 Input Analysis and Evaluation Constraints......Page 83
Application (xAppl)......Page 84
HW Architecture (xArch)......Page 87
Temporal and Spatial Task Mapping (xMap)......Page 88
Stochastic Description (Xi (ti, pej))......Page 91
Constraints (c)......Page 92
6.2 Analysis Algorithm......Page 93
6.2.1 Analysis Graph Calculation......Page 94
6.2.2 Analysis Precalculation......Page 96
6.2.3 Critical Path Evaluation......Page 99
7.1 Overview and Key Components......Page 102
7.2 Virtual Processing Unit Concept......Page 103
7.3 Annotation Principle of Execution Characteristics......Page 106
7.3.1 Statistical Annotation Model......Page 109
7.3.2 Source-Level Annotation Model......Page 110
Profiler-Based Annotation Model......Page 112
Trace-Based Annotation Model......Page 114
7.4.1 Hardware Abstraction Layer......Page 116
7.4.2 Device Drivers......Page 118
7.4.3 Operating System Layer......Page 120
7.4.4 Middleware Layer......Page 126
Operational Semantic......Page 128
Practical Considerations for Task Modeling......Page 129
7.5.2 Graphical Design Entry......Page 132
7.6 Refinement to Instruction Set Simulation......Page 135
7.6.1 Hardware Simulation Model Refinement......Page 136
7.6.3 Automatic Refinement Flow for the Graphical Design Entry......Page 139
Configuration and Initialization......Page 141
7.7 Summary of the Abstract Simulation Model......Page 142
8.1 Task Level Annotation......Page 144
8.1.1 Task Level Analysis Scenario......Page 145
Annotation Results......Page 147
Summary of Task Level Analysis......Page 150
MIL-STD-188-110B......Page 151
Representative Communication Algorithm......Page 152
Combination of Algorithms......Page 153
8.2.2 Overview of Processing Element......Page 154
8.2.3 Exploration......Page 155
Step 1 (Analytical Model): Initial Setup......Page 156
Step 2 (Analytical Model): Single Processor Core Schedule Effects......Page 158
Step 4 (Analytical Model): Replacement of TI C55x with C64x DSP......Page 159
Step 5 (Analytical Model): Task Rescheduling......Page 160
Step 6 (Abstract Simulation Model): Validation of the Implementation Candidate......Page 161
Step 8 (Analytical Model): Tightly Coupled Viterbi CoProcessor......Page 162
Further Exploration Steps and Process......Page 163
8.3 Summary of the Case Study......Page 164
Chapter 9 Summary and Outlook......Page 165
A.1.2 Shortcut Elimination......Page 169
A.1.3 Iterative Application......Page 170
A.2.1 Scheduling Definition Within the Analysis Framework......Page 172
A.4 Practical Calculation and Stochastic Independence......Page 173
B.1 Advanced Device Drivers......Page 175
C.1 Overview......Page 177
C.2 Task Graph Assembly and Analysis......Page 179
C.3 VPU IP Component and Platform Modeling......Page 181
C.4 Task Graph Mapping......Page 182
References......Page 184
Index......Page 198