Subthreshold leakage power is expected to dominate the total power consumption of a CMOS circuit in the near future as depicted in Figure 10. 1 [5], [21], [29], [33]-[37]. Energy-efficient circuit techniques aimed at lowering leakage currents are, therefore, highly desirable. The subthreshold leakage current of a domino logic circuit can vary dramatically with the voltage state of the dynamic and output nodes. The dynamic node voltage dependent asymmetry of the subthreshold leakage current characteristics of dual threshold voltage domino gates was first noted in [136]. Based on this asymmetry, several circuit techniques that place dual threshold voltage domino logic circuits into a low leakage state have been proposed in [34], [130],
[136], and [142].
A quantitative study of the subthreshold leakage current characteristics of standard low threshold voltage (low-V t ) or dual threshold voltage (dual-V t ) domino logic circuits, however, has to date not been presented in the literature. The node voltage-dependent subthreshold leakage current characteristics of domino logic circuits are examined in this chapter. Different subthreshold leakage current conduction paths which occur during different dynamic and output node voltage states are identified. A discharged dynamic node is preferable for reducing leakage current in a dual-V t circuit. Alternatively, a charged dynamic node is preferred for lower subthreshold leakage energy in a standard low-V t domino logic circuit with stacked pull-down devices, such as an AND gate.
Noise immunity issues in dual-V t domino logic circuits are ignored in [136]. Provided that a dual-V t CMOS technology is employed, the noise immunity of domino logic circuits can be significantly degraded, affecting the reliability. A brief discussion of noise immunity-related issues in dual-V t domino circuits is provided in [130]. A dual-V t domino logic circuit technique based on low-V t keeper transistors is described in this chapter to maintain a noise immunity similar to standard low-V t domino logic circuits [130].
A discussion of the effect of dual-V t CMOS technologies on the noise immunity characteristics of domino logic circuits is provided in this chapter. Two different dual-V t domino