Multi-Core Embedded Systems (Embedded Multi-Core Systems)

✍ Scribed by Georgios Kornaros

• Publisher: CRC Press
• Year: 2010
• Tongue: English
• Leaves: 493
• Edition: 1
• Category: Library

✦ Synopsis

Details a real-world product that applies a cutting-edge multi-core architecture Increasingly demanding modern applications—such as those used in telecommunications networking and real-time processing of audio, video, and multimedia streams—require multiple processors to achieve computational performance at the rate of a few giga-operations per second. This necessity for speed and manageable power consumption makes it likely that the next generation of embedded processing systems will include hundreds of cores, while being increasingly programmable, blending processors and configurable hardware in a power-efficient manner. Multi-Core Embedded Systems presents a variety of perspectives that elucidate the technical challenges associated with such increased integration of homogeneous (processors) and heterogeneous multiple cores. It offers an analysis that industry engineers and professionals will need to understand the physical details of both software and hardware in embedded architectures, as well as their limitations and potential for future growth. Discusses the available programming models spread across different abstraction levels The book begins with an overview of the evolution of multiprocessor architectures for embedded applications and discusses techniques for autonomous power management of system-level parameters. It addresses the use of existing open-source (and free) tools originating from several application domains—such as traffic modeling, graph theory, parallel computing and network simulation. In addition, the authors cover other important topics associated with multi-core embedded systems, such as: Architectures and interconnects Embedded design methodologies Mapping of applications Programming paradigms and models of computation Power optimization and reliability issues Performance tools and benchmarks Resource management Multithreading Multi-core programming challenges Compiler and operating system support This is a detailed discussion of research on the interaction between multi-core systems, applications and software views, and processor configuration and extension, which add a new dimension to the problem space. The text offers a useful overview of the most widespread industrial and domain-specific solutions, providing several examples of working implementations.

✦ Table of Contents

Contents......Page 6
List of Figures......Page 14
List of Tables......Page 22
Foreword......Page 24
Preface......Page 26
1. Multi-Core Architectures for Embedded Systems......Page 31
1.1 Introduction......Page 32
1.1.1 What Makes Multiprocessor Solutions Attractive?......Page 33
1.2 Architectural Considerations......Page 39
1.3 Interconnection Networks......Page 41
1.4 Software Optimizations......Page 43
1.5.1 HiBRID-SoC for Multimedia Signal Processing......Page 44
1.5.2 VIPER Multiprocessor SoC......Page 46
1.5.3 Defect-Tolerant and Reconfigurable MPSoC......Page 47
1.5.4 Homogeneous Multiprocessor for Embedded Printer Application......Page 48
1.5.5 General Purpose Multiprocessor DSP......Page 50
1.5.6 Multiprocessor DSP for Mobile Applications......Page 51
1.5.7 Multi-Core DSP Platforms......Page 53
Review Questions......Page 55
Bibliography......Page 57
2. Application-Specific Customizable Embedded Systems......Page 61
2.1 Introduction......Page 62
2.2 Challenges and Opportunities......Page 64
2.2.1 Objectives......Page 65
2.3.1 Customized Application-Specific Processor Techniques......Page 67
2.3.2 Customized Application-Specific On-Chip Interconnect Techniques......Page 70
2.4 Configurable Processors and Instruction Set Synthesis......Page 71
2.4.1 Design Methodology for Processor Customization......Page 73
2.4.2 Instruction Set Extension Techniques......Page 74
2.4.4 Customizing On-Chip Communication Interconnect......Page 78
2.4.5 Customization of MPSoCs......Page 79
2.5 Reconfigurable Instruction Set Processors......Page 82
2.5.1 Warp Processing......Page 83
2.6 Hardware/Software Codesign......Page 84
2.7 Hardware Architecture Description Languages......Page 85
2.7.1 LISATek Design Platform......Page 87
2.8 Myths and Realities......Page 88
2.9 Case Study: Realizing Customizable Multi-Core Designs......Page 90
2.10 The Future: System Design with Customizable Architectures, Software, and Tools......Page 92
Bibliography......Page 93
3. Power Optimization in Multi-Core System-on-Chip......Page 101
3.1 Introduction......Page 102
3.2 Low Power Design......Page 104
3.2.1 Power Models......Page 105
3.2.2 Power Analysis Tools......Page 110
3.3.1 Basic Features......Page 112
3.3.2 Power Models......Page 113
3.3.3 Augmented Signals......Page 114
3.3.4 Power States......Page 115
3.3.5 Application Examples......Page 116
3.4 On-Chip Communication Architectures......Page 117
3.5 NOCEXplore......Page 120
3.5.1 Analysis......Page 121
3.6 DPM and DVS in Multi-Core Systems......Page 125
3.7 Conclusions......Page 130
Review Questions......Page 131
Bibliography......Page 132
4. Routing Algorithms for Irregular Mesh-Based Network-on-Chip......Page 141
4.1 Introduction......Page 142
4.2.2 Irregular Mesh Topology......Page 143
4.3 Fault-Tolerant Routing Algorithms for 2D Meshes......Page 145
4.3.1 Fault-Tolerant Routing Using Virtual Channels......Page 146
4.3.2 Fault-Tolerant Routing with Turn Model......Page 147
4.4 Routing Algorithms for Irregular Mesh Topology......Page 156
4.4.1 Traffic-Balanced OAPR Routing Algorithm......Page 157
4.4.2 Application-Specific Routing Algorithm......Page 162
4.5 Placement for Irregular Mesh Topology......Page 166
4.5.1 OIP Placements Based on Chen and Chiu's Algorithm......Page 167
4.5.2 OIP Placements Based on OAPR......Page 170
4.6 Hardware Efficient Routing Algorithms......Page 173
4.6.1 Turns-Table Routing (TT)......Page 176
4.6.3 Source Routing for Deviation Points (SRDP)......Page 177
4.6.4 Degree Priority Routing Algorithm......Page 178
Bibliography......Page 181
5. Debugging Multi-Core Systems-on-Chip......Page 185
5.1 Introduction......Page 186
5.2.1 Limited Internal Observability......Page 188
5.2.2 Asynchronicity and Consistent Global States......Page 189
5.2.3 Non-Determinism and Multiple Traces......Page 191
5.3 Debugging an SoC......Page 193
5.3.1 Errors......Page 194
5.3.2 Example Erroneous System......Page 195
5.3.3 Debug Process......Page 196
5.4.1 Properties......Page 199
5.4.2 Comparing Existing Debug Methods......Page 201
5.5 CSAR Debug Approach......Page 204
5.5.2 Scan-Based Debug......Page 205
5.5.4 Abstraction-Based Debug......Page 206
5.6.2 Monitors......Page 208
5.6.3 Computation-Specific Instrument......Page 210
5.6.4 Protocol-Specific Instrument......Page 211
5.6.5 Event Distribution Interconnect......Page 212
5.6.7 Debug Data Interconnect......Page 213
5.7.2 Abstractions Used by Debugger Software......Page 214
5.8 Debug Example......Page 220
5.9 Conclusions......Page 223
Bibliography......Page 224
6. System-Level Tools for NoC-Based Multi-Core Design......Page 231
6.1 Introduction......Page 232
6.1.1 Related Work......Page 234
6.2 Synthetic Traffic Models......Page 236
6.3 Graph Theoretical Analysis......Page 237
6.3.1 Generating Synthetic Graphs Using TGFF......Page 239
6.4.1 Application Task Embedding and Quality Metrics......Page 240
6.4.2 SCOTCH Partitioning Tool......Page 244
6.5 OMNeT++ Simulation Framework......Page 246
6.6.1 Application Task Graphs......Page 247
6.6.2 Prospective NoC Topology Models......Page 248
6.6.3 Spidergon Network on Chip......Page 249
6.6.4 Task Graph Embedding and Analysis......Page 251
6.6.5 Simulation Models for Proposed NoC Topologies......Page 253
6.6.6 Mpeg4: A Realistic Scenario......Page 257
6.7 Conclusions and Extensions......Page 261
Review Questions......Page 264
Bibliography......Page 265
7. Compiler Techniques for Application Level Memory Optimization for MPSoC......Page 273
7.1 Introduction......Page 274
7.2 Loop Transformation for Single and Multiprocessors......Page 275
7.3 Program Transformation Concepts......Page 276
7.4 Memory Optimization Techniques......Page 278
7.4.3 Buffer Allocation......Page 279
7.5 MPSoC Memory Optimization Techniques......Page 280
7.5.1 Loop Fusion......Page 281
7.5.2 Comparison of Lexicographically Positive and Positive Dependency......Page 282
7.5.3 Tiling......Page 283
7.5.4 Buffer Allocation......Page 284
7.6.1 Computation Time......Page 285
7.7.1 Parallel Processing Area and Partitioning......Page 286
7.7.2 Modulo Operator Elimination......Page 289
7.7.3 Unimodular Transformation......Page 290
7.8 Case Study......Page 291
7.8.1 Cache Ratio and Memory Space......Page 292
7.9 Discussion......Page 293
7.10 Conclusions......Page 294
Review Questions......Page 295
Bibliography......Page 296
8. Programming Models for Multi-Core Embedded Software......Page 299
8.1 Introduction......Page 300
8.2 Thread Libraries for Multi-Threaded Programming......Page 302
8.3.1 Mutual Exclusion Primitives for Deterministic Output......Page 306
8.3.2 Transactional Memory......Page 308
8.4.1 OpenMP......Page 309
8.4.2 Thread Building Blocks......Page 310
8.4.3 Message Passing Interface......Page 311
8.5 Parallel Programming on Multiprocessors......Page 312
8.6 Parallel Programming Using Graphic Processors......Page 313
8.7 Model-Driven Code Generation for Multi-Core Systems......Page 314
8.7.1 StreamIt......Page 315
8.8 Synchronous Programming Languages......Page 316
8.9.1 Basic Concepts......Page 318
8.9.2 Multi-Core Implementations and Their Compilation Schemes......Page 319
8.10 Declarative Synchronous Language: LUSTRE......Page 320
8.10.2 Multi-Core Implementations from LUSTRE Specifications......Page 321
8.11.1 Basic Concepts......Page 322
8.11.2 Characterization and Compilation of SIGNAL......Page 323
8.11.3 SIGNAL Implementations on Distributed Systems......Page 324
8.11.4 Multi-Threaded Programming Models for SIGNAL......Page 326
8.12 Programming Models for Real-Time Software......Page 329
8.12.1 Real-Time Extensions to Synchronous Languages......Page 330
8.13 Future Directions for Multi-Core Programming......Page 331
Review Questions......Page 332
Bibliography......Page 335
9. Operating System Support for Multi-Core Systems-on-Chips......Page 339
9.1 Introduction......Page 340
9.2 Ideal Software Organization......Page 341
9.3 Programming Challenges......Page 343
9.4.1 Board Support Package......Page 344
9.4.2 General Purpose Operating System......Page 347
9.5.1 Automated Application Code Generation and RTOS Modeling......Page 352
9.5.2 Component-Based Operating System......Page 356
9.6 Pros and Cons......Page 359
9.7 Conclusions......Page 360
Review Questions and Answers......Page 362
Bibliography......Page 363
10. Autonomous Power Management in Embedded Multi-Cores......Page 367
10.1 Introduction......Page 368
10.1.1 Why Is Autonomous Power Management Necessary?......Page 369
10.2.1 Clock Gating......Page 372
10.2.3 Dynamic Voltage and Frequency Scaling......Page 373
10.2.4 Smart Caching......Page 374
10.2.5 Scheduling......Page 375
10.2.6 Commercial Power Management Tools......Page 376
10.3 Power Management and RTOS......Page 377
10.4 Power-Smart RTOS and Processor Simulators......Page 379
10.4.1 Chip Multi-Threading (CMT) Architecture Simulator......Page 380
10.5 Autonomous Power Saving in Multi-Core Processors......Page 381
10.5.1 Opportunities to Save Power......Page 383
10.5.2 Strategies to Save Power......Page 384
10.5.3 Case Study: Power Saving in Intel Centrino......Page 386
10.6.2 Global PMU Algorithm......Page 388
10.7 Conclusions......Page 390
Review Questions......Page 392
Bibliography......Page 393
11. Multi-Core System-on-Chip in Real World Products......Page 399
11.1 Introduction......Page 400
11.2.1 Basic Processor Architecture......Page 401
11.2.3 Peripherals and Hardware Functional Accelerators......Page 403
11.3 Tool Flow......Page 405
11.3.2 C Compiler......Page 406
11.3.3 Design Simulation......Page 408
11.4 picoArray Debug and Analysis......Page 411
11.4.1 Language Features......Page 412
11.4.3 Design Browser......Page 413
11.4.4 Scripting......Page 415
11.4.6 FileIO......Page 417
11.5 Hardening Process in Practice......Page 418
11.5.1 Viterbi Decoder Hardening......Page 419
11.6 Design Example......Page 422
Review Questions......Page 426
Bibliography......Page 427
12. Embedded Multi-Core Processing for Networking......Page 429
12.1 Introduction......Page 430
12.2.1 Multi-Core Embedded Systems for Multi-Service Broadband Access and Multimedia Home Networks......Page 433
12.2.2 SoC Integration of Network Components and Examples of Commercial Access NPUs......Page 435
12.2.3 NPU Architectures for Core Network Nodes and High-Speed Networking and Switching......Page 437
12.3 Programmable Packet Processing Engines......Page 442
12.3.1 Parallelism......Page 443
12.3.2 Multi-Threading Support......Page 448
12.3.3 Specialized Instruction Set Architectures......Page 451
12.4 Address Lookup and Packet Classification Engines......Page 452
12.4.1 Classification Techniques......Page 454
12.4.2 Case Studies......Page 456
12.5 Packet Buffering and Queue Management Engines......Page 461
12.5.1 Performance Issues......Page 463
12.5.2 Design of Specialized Core for Implementation of Queue Management in Hardware......Page 465
12.6 Scheduling Engines......Page 472
12.6.1 Data Structures in Scheduling Architectures......Page 473
12.6.2 Task Scheduling......Page 474
12.6.3 Traffic Scheduling......Page 480
12.7 Conclusions......Page 483
Review Questions and Answers......Page 485
Bibliography......Page 489