Memory Efficient Modular VLSI Architecture for Highthroughput and Low-Latency Implementation of Multilevel Lifting 2-D DWT

✍ Scribed by Mohanty, Basant K.; Meher, Pramod Kumar

• Book ID: 120646017
• Publisher: IEEE
• Year: 2011
• Tongue: English
• Weight: 814 KB
• Volume: 59
• Category: Article
• ISSN: 1053-587X
• DOI: 10.1109/TSP.2011.2109953