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Memory-cell layout as a factor in the single-event-upset susceptibility of submicron dice CMOS SRAM

✍ Scribed by V. Ya. Stenin; I. G. Cherkasov


Book ID
110215479
Publisher
Springer
Year
2011
Tongue
English
Weight
273 KB
Volume
40
Category
Article
ISSN
1063-7397

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