Memory array architecture and decoding scheme for 3 V only sector erasable DINOR flash memory

✍ Scribed by Kobayashi, S.; Nakai, H.; Kunori, Y.; Nakayama, T.; Miyawaki, Y.; Terada, Y.; Onoda, H.; Ajika, N.; Hatanaka, M.; Miyoshi, H.; Yoshihara, T.

• Book ID: 119773982
• Publisher: IEEE
• Year: 1994
• Tongue: English
• Weight: 725 KB
• Volume: 29
• Category: Article
• ISSN: 0018-9200
• DOI: 10.1109/4.280695