In this paper we address the parallel timing simulation of synchronous VLSI designs on a network of workstations (NOWs). We suggest combining cycle based and conventional timing simulation techniques to achieve fast timing simulation even on NOWs which are typically characterized by low bandwidth an
β¦ LIBER β¦
Mapping and parallel simulation of synchronous neural networks on multiprocessors
β Scribed by Thilo Reski
- Publisher
- Elsevier Science
- Year
- 1993
- Weight
- 662 KB
- Volume
- 38
- Category
- Article
- ISSN
- 0165-6074
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