Low-voltage, high-speed CMOS analog latched voltage comparator using the “flipped voltage follower” as input stage
✍ Scribed by Hugues J. Achigui; Christian Fayomi; Daniel Massicotte; Mounir Boukadoum
- Publisher
- Elsevier Science
- Year
- 2011
- Tongue
- English
- Weight
- 573 KB
- Volume
- 42
- Category
- Article
- ISSN
- 0026-2692
No coin nor oath required. For personal study only.
✦ Synopsis
The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode signal detector, followed by a regenerative latch and a Set-Reset (S-R) latch. It is suitable for successive-approximation type's analog-to-digital converters (ADC), but can also be adapted for use in flash-type ADCs. The circuit was fabricated using 0.18 mm CMOS technology, and its measured performance shows 12-bit resolution at 20 MHz comparison rate and 1 V single supply voltage, with a total power consumption of 63.5 mW.