Low-Voltage CMOS RF Frequency Synthesizers

✍ Scribed by Howard Cam Luong, Gerry Chi Tak Leung

• Publisher: Cambridge University Press
• Year: 2004
• Tongue: English
• Leaves: 200
• Category: Library

✦ Synopsis

This book provides architectures and design techniques to enable CMOS frequency synthesizers to operate at low-supply voltage at high frequency with good phase noise and low power consumption. It offers in-depth updates on many of these techniques, and introduces useful guidelines and step-by-step procedures on behavior simulations of frequency synthesizers. Finally, the authors feature four successful prototypes to illustrate potential applications of the architectures and design techniques described. Their work will prove useful for engineers, managers, and researchers working in RFIC design for wireless applications.

✦ Table of Contents

Cover......Page 1
Half-title......Page 3
Title......Page 5
Copyright......Page 6
Contents......Page 7
Figures......Page 9
Tables......Page 15
Preface......Page 17
Acknowledgements......Page 19
1.1. Motivation......Page 21
1.2. Book organization......Page 23
2.1. Introduction......Page 25
2.2. Timing jitter......Page 26
2.3. Phase noise......Page 27
2.4. Phase-locked loop......Page 30
2.4.1. Charge-pump-based phase-locked loop (CP-PLL)......Page 34
2.4.2. Phase noise and jitter of phase-locked loop......Page 36
2.4.3. Spurious tone......Page 38
2.4.4. Settling time......Page 39
2.5.2. Integer-N synthesizer......Page 40
2.5.3. Fractional-N synthesizer......Page 42
2.5.4. Dual-loop synthesizer......Page 44
3.1.1. Ring oscillators......Page 48
3.1.1.1. Circuit implementation......Page 49
3.1.1.2. Phase noise of ring oscillators......Page 52
3.1.2.1. Circuit implementation......Page 53
3.1.2.2. Phase noise of LC oscillators......Page 56
3.1.2.3. Phase-noise analysis......Page 57
3.1.2.4. Quadrature oscillators......Page 58
3.1.2.5. Frequency tuning......Page 61
3.2.1. Source-coupled logic divider with resistive load......Page 64
3.2.2. SCL divider with dynamic load......Page 66
3.2.3. Injection-locked frequency divider......Page 67
3.2.4. True single-phase clock divider......Page 68
3.3. Prescaler......Page 69
3.3.1. Non-programmable prescaler......Page 70
3.3.2. Dual-modulus prescaler......Page 71
3.3.3. Multi-modulus Prescaler......Page 72
3.4.1. Phase detector design......Page 75
3.4.2. Phase–frequency detector design......Page 76
3.5. Charge pump......Page 79
3.6.1. Third-order passive loop filter......Page 83
3.6.2. Active loop filter......Page 84
3.7. Inductor design......Page 86
3.7.1. Fundamentals of on-chip inductors......Page 87
3.7.2. Quality factor (Q) of on-chip inductors......Page 90
3.7.3. Design guidelines for on-chip inductors......Page 93
3.8. Varactor design......Page 94
3.8.1. Quality factor (Q) of capacitors......Page 95
3.8.2. pn-junction varactors......Page 96
3.8.3. Accumulation-mode varactors......Page 97
3.9. Switched-capacitor array (SCA)......Page 98
4.2. System considerations......Page 100
4.3. Voltage-controlled oscillators......Page 101
4.4. Divide-by-2 circuit......Page 102
4.5. High-speed clock buffer......Page 104
4.7. Charge pump......Page 105
5.2. Linear model......Page 108
5.3. Mathematical model......Page 111
5.4. Behavioral model using AC analysis......Page 115
5.5. Behavioral model using transient analysis......Page 117
6.1.1. Output frequency......Page 120
6.1.2. Phase noise......Page 121
6.1.4. Switching time......Page 122
6.1.5. Dual-loop design......Page 123
6.2.1.2. Center frequency and power consumption......Page 124
6.2.1.3. Phase noise......Page 127
6.2.2. Frequency divider N2 and N3......Page 129
6.2.4.1. Architecture......Page 131
6.2.4.2. Output frequency......Page 132
6.2.4.3. Phase noise......Page 133
6.2.5.1. Architecture and system design......Page 134
6.2.6. Charge pumps and loop filter......Page 135
6.3. Experimental results......Page 136
6.3.2. Measurement of varactors......Page 138
6.3.3. Measurement of ring oscillator VCO1......Page 139
6.3.5. Measurement of loop filter......Page 140
6.3.7. Measured spurious tones of the frequency synthesizer......Page 142
6.3.9. Performance evaluation......Page 143
7.1. Introduction......Page 146
7.2. Proposed synthesizer architecture......Page 147
7.3. System specification and consideration......Page 149
7.4.1. LC VCOs......Page 153
7.4.2. Loop filter......Page 154
7.4.4. Phase-frequency detector......Page 156
7.4.5. Prescaler......Page 157
7.4.6. sigma–delta modulator......Page 158
7.4.7. Gain and offset adjustment for SCAs......Page 160
7.5.1. Switchable-capacitor array......Page 161
7.5.3. Inductor layout......Page 162
7.6. Experimental results......Page 165
7.7. Performance summary and evaluation......Page 168
8.1. WLAN overview......Page 172
8.2. Design specification......Page 173
8.3. Synthesizer architecture......Page 174
8.4. Quadrature phase generation......Page 176
8.6.1. Programmable frequency divider......Page 177
8.6.1.2. Divide-by-4......Page 180
8.6.1.3. Phase switching circuits......Page 182
8.6.2. Quadrature LC oscillator......Page 185
8.7.1. Introduction......Page 187
8.7.3. Measurement of the QVCO......Page 188
8.7.4. Measurement of the synthesizer......Page 189
References......Page 193
Index......Page 199