๐”– Bobbio Scriptorium
โœฆ   LIBER   โœฆ

Low test-application time method for EEPLA testing

โœ Scribed by Wei, K.-C.; Liu, B.-D.; Tang, J.J.


Book ID
114448272
Publisher
The Institution of Electrical Engineers
Year
1997
Tongue
English
Weight
385 KB
Volume
144
Category
Article
ISSN
1350-2387

No coin nor oath required. For personal study only.


๐Ÿ“œ SIMILAR VOLUMES


A new testing method for EEPLA
โœ Rajsuman, R. ๐Ÿ“‚ Article ๐Ÿ“… 1994 ๐Ÿ› IEEE ๐ŸŒ English โš– 514 KB
Test response reuse-based SoC core test
โœ Jingbo Shao; Guangsheng Ma; Zhi Yang; Ruixue Zhang ๐Ÿ“‚ Article ๐Ÿ“… 2008 ๐Ÿ› Elsevier Science ๐ŸŒ English โš– 308 KB

This paper presents a novel approach to system-on-a-chip (SoC) core test compression and test scheduling. Every test set is compressed through the test responses of its preceding core in preprocessing step by simulation. Consequently, under our method the test sets contain two parts: (1) the test s

Testing times for the tests
โœ Hay, Alastair ๐Ÿ“‚ Article ๐Ÿ“… 1991 ๐Ÿ› Nature Publishing Group ๐ŸŒ English โš– 394 KB