Low-Noise Low-Power Design for Phase-Locked Loops: Multi-Phase High-Performance Oscillators

✍ Scribed by Feng Zhao, Fa Foster Dai (auth.)

Publisher: Springer International Publishing
Year: 2015
Tongue: English
Leaves: 106
Edition: 1
Category: Library

No coin nor oath required. For personal study only.

✦ Synopsis

This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation. The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage. Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters.

✦ Table of Contents

Front Matter....Pages i-xiii
Introduction....Pages 1-11
Analysis of Quantization Noise Reduction Techniques for Fractional-N PLL....Pages 13-24
A Wide-Band Low Power BiCMOS PLL....Pages 25-39
Design and Analysis of QVCO with Various Coupling Techniques....Pages 41-65
Design and Analysis of A Low Power QVCO with Capacitive-Coupling Technique....Pages 67-94
Conclusions....Pages 95-96

✦ Subjects

Circuits and Systems; Electronics and Microelectronics, Instrumentation; Signal, Image and Speech Processing

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