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Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX

✍ Scribed by Kishine, K.; Ishii, K.; Ichino, H.


Book ID
119776004
Publisher
IEEE
Year
2002
Tongue
English
Weight
311 KB
Volume
37
Category
Article
ISSN
0018-9200

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