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Loop-based interconnect modeling and optimization approach for multigigahertz clock network design

✍ Scribed by Xuejue Huang; Restle, P.; Bucelot, T.; Yu Cao; Tsu-Jae King; Chenming Hu

Book ID: 119799083
Publisher: IEEE
Year: 2003
Tongue: English
Weight: 706 KB
Volume: 38
Category: Article
ISSN: 0018-9200
DOI: 10.1109/jssc.2002.808313

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