Logic Circuit Design: Selected Topics and Methods

✍ Scribed by Shimon P. Vingron

• Publisher: Springer
• Year: 2023
• Tongue: English
• Leaves: 237
• Category: Library

✦ Synopsis

The 2^nd edition has been thoroughly revised and is intended as a wakeup call in the stagnant and dormant field of switching algebra and logic circuit design. It presents the material in a concise but thorough way. The topics selected are an in-depth presentation of switching algebra, a theory of memory circuits (sometimes called flop flops), a new approach to asynchronous circuits, and a newly added part presenting a unique programming technique (or language) for programmable logic controllers (PLCs). Be ready for the unorthodox and controversial.

✦ Table of Contents

Preface
Contents
Part I Combinational Circuits and Switching Algebra
Introduction to Part I
1 Logic Variables & Events
1.1 Specifying a Circuit in Plain Prose
1.2 Analogue and Binary Timing Diagrams
1.3 Events Graph and Events Table
1.4 Logic Variables and Logic Formulas
1.5 Drawing the Logic Circuit
2 Switching Devices
2.1 Pneumatic Valves
2.2 Electric Relays
Inverting a Relay Circuit
Realising Feedback
2.3 CMOS Transistors
3 Elementary Logic Functions
3.1 Logic Functions
3.2 Basic Gates
3.3 Using AND, OR and NOT
3.4 Basic Laws
3.5 Single-Variable Formulas
3.6 Commutative and Associative Laws
3.7 Distributive Laws
3.8 Generalised DeMorgan Theorems
3.9 Tautologies and Truth Tables
4 Normal Forms and Circuit Design
4.1 Minterms and Maxterms
4.2 Canonical Normal Forms
4.3 Using Canonical Normal Forms
4.4 Zhegalkin Normal Form
4.5 Dual Zhegalkin Normal Form
5 Veitch-Karnaugh Maps
5.1 How to Draw a Veitch-Karnaugh Map
5.2 Karnaugh Set and Generalised Minterms
5.3 Proving and Developing Theorems
5.4 Evaluating Veitch-Karnaugh maps
5.5 Karnaugh Trees & Map-Entered Variables
6 Adjacency and Consensus
6.1 Adjacent K-Sets and their Consensus
6.2 Formalising Adjacency
6.3 Formalising Consensus
6.4 When is one K-set a Subset of another?
7 Algebraic Minimisation
7.1 Finding the Full Cover
7.2 Finding Minimal Covers
7.3 Minimisation considering Don't Cares
8 Design by Composition
8.1 The Basic Concept
8.2 Catenation
8.3 Visualising the Composition Problem
8.4 Choosing a Generic Function
8.5 Composing an Example Circuit
Reviewing Part I
Part II Theory of Latches
Introduction to Part II
9 Basic Theory of Latches
9.1 What is a Latch?
9.2 The Memory Function
Specifying a Memory Function in a VK-map
Reading the Reduced VK-map of a Memory Function
9.3 Introducing Inclusions and Exclusions
9.4 Basic Memory Evaluation-Formulas
9.5 Generalised Memory Evaluation-Formulas
10 Designing Feedback Latches
10.1 Feedback Evaluation-Formulas
10.2 Memorisation Hazards
Memorisation Hazards in Disjunctive Latches
Memorisation Hazards in Conjunctive Latches
10.3 Delayed Feedback
10.4 Fail-Safe Latch Design
10.5 Fail-Safe Latches with Mutually Inverted Outputs
11 Designing Latches by Composition
11.1 Theory of Latch Composition
11.2 Example Illustrating Latch Composition
11.3 Eccles-Jordan Latch
11.4 Using Eccles-Jordan as a Hinge Latch
Reviewing Part II
Part III Asynchronous Circuits
Introduction to Part III
12 Specifying Asynchronous Circuits
12.1 Developing an Events Graph
12.2 What is an Events Tree?
12.3 What is a Flow Table?
13 Employing Events Trees
13.1 From Events Graph to Events Tree
13.2 Calculating and Drawing the Circuit
13.3 Direct Specification of Feedback
13.4 Verification versus Reverse Engineering
14 Flow Table Development and Usage
14.1 Direct Specification of a Flow Table
14.2 Events Graph to Flow Table
Vingron — Deterministic Sub-Sequences of Input Events
Sandige — Transmitting all Columns of the Events Graph
14.3 Circuit Design by Iterative Catenation
14.4 Compound Self-Reference Table
14.5 When Are Two Flow Tables Equivalent?
Reviewing Part III
Part IV OCTOPUS — A Programming Language for PLCs
Introduction to Part IV
15 Historical Remarks and Programming Overview
15.1 IEC 61131-3 Programming Languages
15.2 The Precursor to OCTOPUS
15.3 Basic Modules of an OCTOPUS Circuit
15.4 Circuit Development using Templates
15.5 Distributed Intelligence of OCTOPUS
16 Designing and Testing on a Computer
16.1 Development Platform logi.CAD
16.2 Modelling Actuators
17 Sequential Function Chart and Sequential Chain
17.1 Sequential Function Chart
17.2 OCTOPUS'S Sequential Chain
17.3 Multi-Path Programs
17.4 Choosing Alternative Paths
17.5 Repeating Sub-Cycles
18 Operating a Transition Controlled Process
18.1 Input Commands and State Visualisation
18.2 Automatic Mode of Operation
18.3 Interrupt, Continue, Next Step
18.4 Manual Mode and False Transition Signal
18.5 Emergency Stop
18.6 Reset
19 The SCV-Module
19.1 SCV-Circuit and Display Panel Layout
19.2 Input Control Commands and Status Visualisation
20 Actuator Control Units
20.1 ACUs for Identity Actuators
20.2 ACUs for Memory Actuators
20.3 On the Usage of the FS Output Signals
Reviewing Part IV
Correction to: Logic Circuit Design
Correction to:Chapters 1 and 2 in: S. P. Vingron, Logic Circuit Design,https://doi.org/10.1007/978-3-031-40673-7
Bibliography
Selected Books
Selected Papers
Backmatter
Index