Layer assignment for VLSI interconnect delay minimization: M.J. Ciesielski (Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst. MA, USA IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (USA). vol. 8, no. 6, p. 702–707 (June 1989)

• Book ID: 103270477
• Publisher: Elsevier Science
• Year: 1990
• Tongue: English
• Weight: 177 KB
• Volume: 21
• Category: Article
• ISSN: 0026-2692
• DOI: 10.1016/0026-2692(90)90083-f