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[Japan Soc. Appl. Phys 2001 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (12-14 June 2001)] 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184) - Impact of CMOS process scaling and SOI on the soft error rates of logic processes

✍ Scribed by Hareland, S.; Maiz, J.; Alavi, M.; Mistry, K.; Walsta, S.; Changhong Dai,

Book ID: 121237780
Publisher: Japan Soc. Appl. Phys
Year: 2001
Tongue: Japanese
Weight: 212 KB
Category: Article
ISBN-13: 9784891140120
DOI: 10.1109/VLSIT.2001.934953

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