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[Japan Soc. Appl. Phys 1995 Symposium on VLSI Technology. Digest of Technical Papers - Kyoto, Japan (6-8 June 1995)] 1995 Symposium on VLSI Technology. Digest of Technical Papers - A channel engineering combined with channel epitaxy optimization and TED suppression for 0.15 μm n-n gate CMOS technology

✍ Scribed by Abiko, H.; Ono, A.; Ueno, R.; Masuoka, S.; Shishiguchi, S.; Nakajima, K.; Sakai, I.

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