IPC-2221: Generic Standard on Printed Board Design (IPC-2221B)

✍ Scribed by IPC

• Publisher: IPC
• Year: 2012
• Tongue: English
• Leaves: 184
• Edition: Revision B
• Category: Library

✦ Synopsis

IPC-2221B is the foundation design standard for all documents in the IPC-2220 series. It establishes the generic requirements for the design of printed boards and other forms of component mounting or interconnecting structures, whether single-sided, double-sided or multilayer. Among the many updates to Revision B are new criteria for conductor characteristics, surface finishes, via protection, board electrical test, dielectric properties, board housings, thermal stress, compliant pins, panelization and internal and external foil thicknesses. Appendix A provides new test coupon designs used for lot acceptance and quality conformance testing.

✦ Table of Contents

TABLE OF CONTENTS
CONTENTS
1 SCOPE
1.1 Purpose
1.2 Documentation Hierarchy
1.3 Presentation
1.3.1 Dimensional Units
1.4 Interpretation
1.5 Definition of Terms
1.5.1 Microvia
1.6 Classification of Products
1.6.1 Printed Board Type
1.6.2 Performance Classification
1.6.3 Producibility Level
1.7 Revision Level Changes
2 APPLICABLE DOCUMENTS
2.1 IPC
2.2 Joint Industry Standards
2.3 Society of Automotive Engineers
2.4 American Society for Testing and Materials
2.5 Underwriters Labs
2.6 IEEE
2.7 ANSI
2.8 ANSI/ESD
2.9 PCMCIA
3 GENERAL REQUIREMENTS
3.1 Information Hierarchy
3.1.1 Order of Precedence
3.1.2 End-Product Performance Requirements
3.2 Design Considerations
3.3 Schematic/Logic Diagram
3.4 Density Evaluation
3.5 Parts List
3.6 Test Requirement Considerations
3.6.1 Electrical
3.6.1.1 Bare Printed Board Testing
3.6.1.2 Test Methods
3.6.1.2.1 HiPot Testing
3.6.1.2.2 Impedance Considerations
3.6.1.3 Test Data (Source Data)
3.6.2 Printed Board Assembly Testability
3.6.3 Boundary Scan Testing
3.6.4 Functional Test Concern for Printed Board Assemblies
3.6.4.1 Test Connectors
3.6.4.2 Initialization and Synchronization
3.6.4.3 Long Counter Chains
3.6.4.4 Self Diagnostics
3.6.4.5 Physical Test Concerns
3.6.5 In-Circuit Test Concerns for Printed Board Assemblies
3.6.5.1 In-Circuit Test Fixtures
3.6.5.2 In-Circuit Test Electrical Considerations
3.6.6 Mechanical
3.6.6.1 Uniformity of Connectors
3.6.6.2 Uniformity of Power Distribution Arrangement and Signal Levels on Connectors
3.7 Layout Evaluation
3.7.1 Printed Board Layout Design
3.7.1.1 Layout Concepts
3.7.2 Feasibility Density Evaluation
4 MATERIALS
4.1 Material Selection
4.1.1 Material Selection for Structural Strength
4.1.2 Material Selection for Electrical Properties
4.1.3 Material Selection for Environmental Properties
4.2 Dielectric Base Materials (Including Prepregs and Adhesives)
4.2.1 Preimpregnated Bonding Layer (Prepreg)
4.2.2 Adhesives
4.2.2.1 Epoxies
4.2.2.2 Silicone Elastomers
4.2.2.3 Acrylics
4.2.2.4 Polyurethanes
4.2.2.5 Specialized Acrylate-Based Adhesives
4.2.2.6 Other Adhesives
4.2.3 Adhesive Films or Sheets
4.2.4 Electrically Conductive Adhesives
4.2.5 Thermally Conductive/Electrically Insulating Adhesives
4.2.5.1 Epoxies
4.2.5.2 Silicone Elastomers
4.2.5.3 Urethanes
4.2.5.4 Use of Structural Adhesives as Thermal Adhesives
4.3 Laminate Materials
4.3.1 High Tg Laminates
4.3.2 Color Pigmentation
4.3.3 Dielectric Thickness/Spacing
4.3.4 Thermally Conductive Laminates
4.3.5 Minimum Base Material Thickness for PC Card Form Factors
4.4 Conductive Materials
4.4.1 Electroless Copper Plating
4.4.2 Semiconductive Coatings
4.4.3 Electrolytic Copper Plating
4.4.4 Gold Plating
4.4.4.1 Electroless Nickel/Immersion Gold (ENIG)
4.4.4.2 Electroless Nickel/Immersion Gold/Electroless Gold (ENIG/EG)
4.4.4.3 Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG)
4.4.5 Immersion Silver
4.4.6 Immersion Tin
4.4.7 Organic Solderability Preservative (OSP)
4.4.8 Nickel Plating
4.4.9 Tin/Lead Plating
4.4.9.1 Tin Plating
4.4.10 Solder Coating
4.4.10.1 Hot Air Solder Leveling (HASL)
4.4.10.1.1 Tin Lead HASL
4.4.10.1.2 Lead-free HASL
4.4.11 Other Metallic Coatings for Edge Printed Board Contacts
4.4.12 Metallic Foil/Film
4.4.12.1 Copper Foil
4.4.12.2 Copper Film
4.4.12.2.1 Resin Coated Copper Foil
4.4.12.2.1.1 Copper Foil With Single Layers of Resin
4.4.11.2.1.2 Copper Foil With Two Layers of Resin
4.4.12.3 Other Foils/Film
4.4.12.4 Metal Core Substrates
4.5 Electronic Component Materials
4.5.1 Embedded (Buried) Resistors
4.5.2 Embedded (Buried) Capacitors
4.5.3 Embedded (Buried Inductors)
4.6 Organic Protective Coatings
4.6.1 Solder Mask Coatings
4.6.1.1 Mask Adhesion and Coverage
4.6.1.2 Mask Clearances and Dams
4.6.2 Conformal Coatings
4.6.2.1 Conformal Coating Types and Thickness
4.6.3 Tarnish Protective Coatings
4.7 Marking and Legends
4.7.1 ESD Considerations
5 MECHANICAL/PHYSICAL PROPERTIES
5.1 Fabrication Considerations
5.1.1 Bare Printed Board Fabrication
5.2 Product/Printed Board Configuration
5.2.1 Printed Board Type
5.2.2 Printed Board Size
5.2.3 Printed Board Geometries (Size and Shape)
5.2.3.1 Material Size
5.2.4 Bow and Twist
5.2.4.1 Bow and Twist for PC Card Form Factor Printed Boards
5.2.5 Structural Strength
5.2.6 Composite (Constraining-Core) Printed Boards
5.2.7 Vibration Design
5.3 Assembly Requirements
5.3.1 Mechanical Hardware Attachment
5.3.2 Part Support
5.3.3 Assembly and Test
5.3.4 Tooling Rails for PC Card Form Factor Printed Boards
5.4 Dimensioning Systems
5.4.1 Dimensions and Tolerances
5.4.2 Component and Feature Location
5.4.2.1 Grid Systems
5.4.2.2 Gridless Systems
5.4.3 Datum Features
5.4.3.1 Datum Features for Palletization
5.5 Printed Board Thickness Tolerance
5.6 Panelization
5.7 Palletization
6 ELECTRICAL PROPERTIES
6.1 Electrical Considerations
6.1.1 Electrical Performance
6.1.2 Power Distribution Considerations
6.1.3 Circuit Type Considerations
6.1.3.1 Digital Circuits
6.1.3.2 Analog Circuits
6.2 Conductive Material Requirements
6.3 Electrical Clearance
6.3.1 B1-Internal Conductors
6.3.2 B2-External Conductors, Uncoated, Sea Level to 3050 m [10,007 feet]
6.3.3 B3-External Conductors, Uncoated, Over 3050 m [10,007 feet]
6.3.4 B4-External Conductors, with Permanent Polymer Coating (Any Elevation)
6.3.5 A5-External Conductors, with Conformal Coating over Assembly (Any Elevation)
6.3.6 A6-External Component Lead/Termination, Uncoated, Sea Level to 3050 m [10,007 feet]
6.3.7 A7-External Component Lead/Termination, with Conformal Coating (Any Elevation)
6.4 Impedance Controls
6.4.1 Microstrip
6.4.2 Embedded Microstrip
6.4.3 Stripline Properties
6.4.4 Asymmetric Stripline Properties
6.4.5 Capacitance Considerations
6.4.6 Inductance Considerations
7 THERMAL MANAGEMENT
7.1 Cooling Mechanisms
7.1.1 Conduction
7.1.2 Radiation
7.1.3 Convection
7.1.4 Altitude Effects
7.2 Heat Dissipation Considerations
7.2.1 Printed Board Housings
7.2.1.1 Enclosed Housing
7.2.1.2 Ventilated Housing
7.2.2 Individual Component Heat Dissipation
7.2.3 Thermal Management Considerations for Printed Board Heatsinks
7.2.4 Assembly of Heatsinks to Printed Boards
7.2.5 Special Design Considerations for SMT Printed Board Heatsinks
7.3 Heat Transfer Techniques
7.3.1 Coefficient of Thermal Expansion (CTE) Characteristics
7.3.2 Thermal Transfer
7.3.3 Thermal Matching
7.4 Thermal Design Reliability
8 COMPONENT AND ASSEMBLY ISSUES
8.1 General Placement Requirements
8.1.1 Automatic Assembly
8.1.1.1 Printed Board Size
8.1.1.2 Mixed Assemblies
8.1.1.3 Surface Mounting
8.1.2 Component Placement
8.1.3 Orientation
8.1.4 Accessibility
8.1.5 Design Envelope
8.1.6 Component Body Centering
8.1.7 Flush Mounting Over Conductive Areas
8.1.8 Clearances
8.1.9 Physical Support
8.1.9.1 Component Mounting Techniques for Shock and
Vibration
8.1.9.1.1 Filleting
8.1.9.2 Class 3 High Reliability Applications
8.1.10 Heat Dissipation
8.1.11 Stress Relief
8.2 General Attachment Requirements
8.2.1 Through-Hole
8.2.2 Surface Mounting
8.2.3 Mixed Assemblies
8.2.4 Soldering Considerations
8.2.4.1 Thermal Stress Methodologies
8.2.5 Connectors and Interconnects
8.2.5.1 One-Part Connectors
8.2.5.2 Dual In-line Connectors
8.2.5.3 Edge Printed Board Connectors
8.2.5.4 Two-Part Multiple Connectors
8.2.5.5 Two-Part Discrete-Contact Connectors
8.2.5.6 Edge Printed Board Adapter Connectors
8.2.6 Fastening Hardware
8.2.7 Stiffeners
8.2.8 Lands for Flattened Round Leads
8.2.9 Solder Terminals
8.2.9.1 Terminal Mounting-Mechanical
8.2.9.2 Terminal Mounting-Electrical
8.2.9.3 Attachment of Wires/Leads to Terminals
8.2.10 Eyelets
8.2.11 Special Wiring
8.2.11.1 Jumper Wires
8.2.11.2 Types
8.2.11.3 Application
8.2.12 Heat Shrinkable Devices
8.2.13 Bus Bar
8.2.14 Flexible Cable
8.3 Through-Hole Requirements
8.3.1 Leads Mounted in Through-Holes
8.3.1.1 Straight Through-Hole Mounted Leads
8.3.1.2 Unclinched Leads
8.3.1.3 Clinched Leads
8.3.1.4 Partially Clinched
8.3.1.5 Dual In-line Packages
8.3.1.6 Axial Leaded Components
8.3.1.7 Radial-Lead Components
8.3.1.8 Perpendicular (Vertical) Mounting
8.3.1.9 Flat-Packs
8.3.1.10 Metal Power Packages
8.4 Standard Surface Mount Requirements
8.4.1 Surface-Mounted Leaded Components
8.4.2 Flat-Pack Components
8.4.3 Ribbon Lead Termination
8.4.4 Round Lead Termination
8.4.5 Component Lead Sockets
8.5 Fine Pitch SMT (Peripherals)
8.6 Bare Die
8.6.1 Wire Bond
8.6.2 Flip Chip
8.6.3 Chip Scale
8.7 Tape Automated Bonding
8.8 Grid Array SMT
8.9 No-Lead Devices
8.9.1 Small Outline and Quad Flat No Lead with Pullback Leads (PQFN, PSON)
8.10 Compliant Pin Design Guidelines
9 HOLES/INTERCONNECTIONS
9.1 General Requirements for Lands with Holes
9.1.1 Land Requirements
9.1.2 Annular Ring Requirements
9.1.2.1 External Annular Ring
9.1.2.2 Internal Annular Ring
9.1.3 Thermal Relief in Conductor Planes
9.1.4 Lands for Flattened Round Leads
9.2 Holes
9.2.1 Unsupported Holes
9.2.1.1 Tooling Holes
9.2.1.2 Mounting Holes
9.2.2 Plated Holes
9.2.2.1 Blind Vias
9.2.2.2 Buried Vias
9.2.2.3 Hole Size of Blind and Buried Vias
9.2.2.4 Thermal Vias
9.2.2.5 Compliant Pin Systems
9.2.2.5.1 Compliant Pin System Considerations
9.2.3 Location
9.2.5 Location Tolerances
9.2.5.1 NPTH Tolerances
9.2.5.1.1 Tooling Holes
9.2.5.1.2 Mounting Holes
9.2.5.2 PTH Tolerances
9.2.5.2.1 Plated-Through Hole Tolerances
9.2.5.2.2 Printed Board Mounting Holes
9.2.6 Quantity
9.2.7 Spacing of Adjacent Holes
9.2.8 Aspect Ratio
9.3 Via Protection
9.3.1 Via Protection Requirements
9.3.2 Via Fill
10 GENERAL CIRCUIT FEATURE REQUIREMENTS
10.1 Conductor Characteristics
10.1.1 Conductor Width and Thickness
10.1.2 Electrical Clearance
10.1.3 Conductor Routing
10.1.4 Conductor Spacing
10.1.5 Plating Thieves
10.2 Land Characteristics
10.2.1 Manufacturing Allowances
10.2.2 Lands for Surface Mounting
10.2.3 Test Points
10.2.4 Orientation Symbols
10.3 Large Conductive Areas
11 DOCUMENTATION
11.1 Special Tooling
11.2 Layout
11.2.1 Viewing
11.2.2 Accuracy and Scale
11.2.3 Layout Notes
11.2.4 Automated-Layout Techniques
11.3 Deviation Requirements
11.4 Phototool Considerations
11.4.1 Artwork Master Files
11.4.2 Film Base Material
11.4.3 Solder Mask Coating Phototools
12 QUALITY ASSURANCE
12.1 Conformance Test Coupons
12.2 Material Quality Assurance
12.2.1 Laminates
12.2.2 Compliant Pin
12.3 Conformance Evaluations
12.3.1 Coupon Quantity and Location
12.3.2 Coupon Identification
12.3.3 General Coupon Requirements
12.3.3.1 Tolerances
12.3.3.2 Etched Letters
12.3.3.3 Interlayer Connection Holes
12.3.3.4 Metal Cores
12.4 Individual Coupon Design
12.4.1 Plated Hole Evaluation (Thermal Stress, Rework Simulation, Registration) Coupons
12.4.1.1 AB/R Coupon
12.4.1.2 Legacy A, B or A/B Coupons
12.4.2 Moisture and Insulation Resistance Coupons
12.4.2.1 E Coupon
12.4.2.2 Legacy E Coupon
12.4.3 Hole Solderability Coupons
12.4.3.1 S Coupon
12.4.3.2 Legacy S Coupon
12.4.4 Surface Mount Solderability Coupons
12.4.4.1 W Coupon
12.4.4.2 Legacy M Coupon
12.4.5 Interconnect Resistance and Continuity Coupons
12.4.5.1 D Coupon
12.4.5.2 Legacy D Coupon
12.4.6 Solder Mask Adhesion Coupons
12.4.6.1 G Coupon
12.4.6.2 Legacy G Coupon
12.4.7 Surface Insulation Resistance Coupons
12.4.7.1 H Coupon
12.4.7.2 Legacy H Coupon
12.4.8 Peel Strength and Plating Adhesion Coupons
12.4.8.1 P Coupon
12.4.8.2 Legacy C Coupon
12.4.9 Controlled Impedance Coupons
12.4.9.1 Z Coupon
12.4.10 Optional Legacy Registration Coupons
12.4.11 Legacy N Coupon (Peel Strength, Surface Mount Bond Strength - Optional for SMT)
12.4.12 Coupon X (Bending Flexibility and Endurance,
Flexible Printed Board
12.4.13 Process Control Test Coupon
APPENDICES
APPENDIX A
APPENDIX B
APPENDIX C
Example of a Testability Design Checklist
FIGURES
Figure 1-1 Microvia Definition
Figure 3-1 Package Size and I/O Count
Figure 3-2 Test Land Free Area for Parts and Other
Figure 3-3 Test Land Free Area for Tall Parts
Figure 3-4 Probing Test Lands
Figure 3-5 Example of Usable Area Calculation, mm
Figure 3-6 Printed Board Density Evaluation
Figure 4-1 HASL Surface Topology Comparison
Figure 5-1 Example of Printed Board Size Standardization, mm [in]
Figure 5-2 Typical Asymmetrical Constraining-Core
Configuration
Figure 5-3A Multilayer Metal Core Printed Board with
Two Symmetrical Copper-Invar-Copper Constraining
Cores
Figure 5-3B Symmetrical Constraining Core Printed
Board with a Copper-Invar-Copper Center Core
Figure 5-4 Advantages of Positional Tolerance Over Bilateral Tolerance,
Figure 5-5 Datum Reference Frame
Figure 5-6 Example of Location of a Pattern of PTHs, mm [in]
Figure 5-7 Example of a Pattern of Tooling/Mounting Holes, mm [in]
Figure 5-8 Example of Location of a Conductor Pattern Using Fiducials,
Figure 5-9 Example of Printed Board Profile Location and Tolerance,
Figure 5-10 Example of a Printed Board Drawing Utilizing Geometric Dimensioning and Tolerancing,
Figure 5-11 Fiducial Clearance Requirements
Figure 5-12 Printed Board Panelization/Palletization, mm
Figure 5-13 Example of Connector Key Slot Location and Tolerance, mm [in]
Figure 6-1 Voltage/Ground Distribution Concepts
Figure 6-2 Single Reference Edge Routing
Figure 6-3 Circuit Distribution
Figure 6-4 Transmission Line Printed Board Construction
Figure 6-5 Capacitance vs. Conductor Width and Dielectric Thickness for Microstrip Lines, mm [in]
Figure 6-6 Capacitance vs. Conductor Width and Spacing for Striplines,
Figure 6-7 Single Conductor Crossover
Figure 7-1 Component Clearance Requirements for Automatic Component Insertion
Figure 7-2 Relative Coefficient of Thermal Expansion (CTE) Comparison
Figure 8-1 Component Orientation for Boundaries and/or Wave Solder Applications
Figure 8-2 Component Body Centering
Figure 8-3 Axial-Leaded Component Mounted Over
Conductors
Figure 8-4 Uncoated Board Clearance
Figure 8-5 Clamp-Mounted Axial-Leaded Component
Figure 8-6 Adhesive-Bonded Axial-Leaded Component
Figure 8-7 Example of Filleting Compared to Bonding
Figure 8-8 Mounting with Feet or Standoffs
Figure 8-9 Heat Dissipation Examples
Figure 8-10 Lead Bends
Figure 8-11 Typical Lead Configurations
Figure 8-12 Typical Keying Arrangement
Figure 8-13 Printed Board Edge Tolerancing
Figure 8-14 Lead-In Chamfer Configuration
Figure 8-15 Two-Part Connector
Figure 8-16 Edge-Board Adapter Connector
Figure 8-17 Round or Flattened (Coined) Lead Joint Description
Figure 8-18 Standoff Terminal Mounting, mm [in]
Figure 8-19 Dual Hole Configuration for Interfacial and Interlayer Terminal Mountings
Figure 8-20 Partially Clinched Through-Hole Leads
Figure 8-21 Dual In-Line Package (DIP) Lead Bends
Figure 8-22 Solder in the Lead Bend Radius
Figure 8-23 Two-Lead Radial-Leaded Components
Figure 8-24 Radial Two-Lead Component Mounting, mm [in]
Figure 8-25 Meniscus Clearance, mm [in]
Figure 8-26 ‘‘TO’’ Can Radial-Leaded Component, mm [in]
Figure 8-27 Perpendicular Part Mounting, mm [in]
Figure 8-28 Flat-Packs and Quad Flat-Packs
Figure 8-29 Examples of Configuration of Ribbon Leads for
Through-Hole Mounted Flat-Packs
Figure 8-30 Metal Power Packages with Compliant Leads
Figure 8-31 Metal Power Package with Resilient Spacers
Figure 8-32 Metal Power Package with Noncompliant Leads
Figure 8-33 Examples of Flat-Pack Surface Mounting
Figure 8-34 Round or Coined Lead
Figure 8-35 Configuration of Ribbon Leads for Planar Mounted Flat-Packs
Figure 8-36 Heel Mounting Requirements
Figure 8-37 TSSOP Package Construction
Figure 8-38 SQFP Package Construction
Figure 8-39 Examples of Ball Grid Array (BGA) Package
Construction
Figure 8-40 Ceramic Column Grid Array (CGA) Package
Construction
Figure 8-41 Land Grid Array (LGA) Package Construction
Figure 8-42 Quad Flat No-Lead (QFN)
Construction
Figure 8-43 Small Outline No-lead (SON)
Construction
Figure 8-44 Pullback Quad Flat No Lead
(PQFN) Construction
Figure 9-1 Examples of Modified Land Shapes
Figure 9-2 External Annular Ring
Figure 9-3 Internal Annular Ring
Figure 9-4 Typical Thermal Relief in Planes
Figure 10-1 Etched Conductor Characteristics
Figure 10-2 Example of Conductor
Beef-Up or Neck-Down
Figure 10-3 Conductor Optimization Between Lands
Figure 11-1 Flow Chart of Printed Board Design/Fabrication Sequence
Figure 11-2 Multilayer Printed Board Viewing
Figure 11-3 Gang Solder Mask Window
Figure 11-4 Pocket Solder Mask Window
Figure 12-1 Panel Utilization among IPC-2221B Conformance Coupon Designs
Figure 12-2 Panel Utilization among Legacy Conformance Coupon Designs
Figure 12-3 Example Stack-up for a Ten Layer Printed Board
Figure 12-4 Systematic Path for Implementation of
Statistical Process Control (SPC)
Figure A.2-1 AB/R Coupon Layout, mm [in]
Figure A.2-2 AB/R Coupon Example Layers
Figure A.3-1 A/R Coupon Layout, mm [in]
Figure A.3-2 A/R Coupon Example Layers
Figure A.4-1 B/R Coupon Layout, mm [in]
Figure A.5-1 E Coupon Layout, mm [in]
Figure A.5-2 E Coupon
Figure A.6-1 S Coupon Layout, mm [in]
Figure A.6-2 S Coupon Example Layers
Figure A.7-1 W Coupon Layout, mm [in]
Figure A.7-2 W Coupon Layout
Figure A.8-1 D Coupon Layout with A and B Features, mm [in]
Figure A.8-2 D Coupon Example Layers with A and B Features
Figure A.8-3 D Coupon Layout with Non-through Via B Features, mm [in]
Figure A.9-1 G Coupon Layout, mm [in]
Figure A.9-2 G Coupon Example Layers
Figure A.10-1 H Coupon Layout, mm [in]
Figure A.10-2 H Coupon Example Layers
Figure A.11-1 P Coupon Layout, mm [in]
Figure A.11-2 P Coupon Example Layers
Figure A.12-1 Z Coupon Layout (Microstrip and edge-coupled microstrip), mm [in]
Figure A.12-2 Z Coupon Example Layers
Figure A.12-3 Z Coupon Layout (Microstrip and edge-coupled microstrip using alternative test points), mm [in]
Figure B.2-1 Test Coupons A and B, mm [in]
Figure B.2-2 Test Coupons A and B (Conductor Detail), mm [in]
Figure B.2-3 Test Coupon A/B, mm [in]
Figure B.2-4 Test Coupon A/B (Conductor Detail), mm [in]
Figure B.3-1 Coupon E, mm
Figure B.3-2 ‘‘Y’’ Pattern for Chip Component Cleanliness Test Pattern
Figure B.4-1 Test Coupon S, mm [in]
Figure B.5-1 Test Coupon M, Surface Mounting Solderability Testing, mm [in]
Figure B.6-1 Test Coupon D, mm [in]
Figure B.6-2 10 Layer Example
Figure B.6-3 Example of a 10 Layer Coupon D, Modified to Include Blind and Buried Vias
Figure B.6-4 Test Coupon D for Process Control of 4 Layer Printed Boards
Figure B.7-1 Test Coupon G, Solder Resist Adhesive, mm [in]
Figure B.8-1 Optional Coupon H, mm [in]
Figure B.8-2 Comb Pattern Examples
Figure B.9-1 Coupon C, External Layers Only, mm [in]
Figure B.10-1 Test Coupon F, mm [in]
Figure B.10-2 Test Coupon R, mm [in]
Figure B.10-3 Worst-Case Hole/Land Relationship
Figure B.11-1 Test Coupon N, Surface Mounting Bond Strength and Peel Strength, mm [in]
Figure B.12-1 Test Coupon X, mm [in]
Figure B.12-2 Bending Test
TABLES
Table 3-1 PCB Design/Performance Tradeoff Checklist
Table 3-2 Component Grid Areas
Table 4-1 Typical Properties of Common Dielectric Materials
Table 4-2 Final Finish and Coating Requirements
Table 4-3 Surface and Hole Copper Plating Minimum Requirements
for Buried Vias >2 Layers, Through-Holes, and Blind Vias
Table 4-4 Surface and Hole Copper Plating Minimum
Requirements for Microvias (Blind and Buried)
Table 4-5 Surface and Hole Copper Plating Minimum
Requirements for Buried Via Cores (2 Layers)
Table 4-6 Surface Finishes
Table 4-7 Gold Plating Uses
Table 4-8 ENIG Surface Finish Advantages and Disadvantages
Table 4-9 ENIG/EG Surface Finish Advantages and Limitations
Table 4-10 ENEPIG Surface Finish Advantages and Disadvantages
Table 4-11 Immersion Silver Surface Finish Advantages and Disadvantages
Table 4-12 Immersion Tin Surface Finish Advantages and Disadvantages
Table 4-13 OSP Surface Finish Advantages and Limitations
Table 4-14 Copper Foil/Film Requirements
Table 4-15 Metal Core Substrates
Table 4-16 Typical Minimum Solder Mask Clearances and Dams
Table 4-17 Conformal Coating Types and Thickness Range
Table 4-18 Conformal Coating Functionality
Table 5-1 Fabrication Assumptions and Considerations
Table 5-2 PC Card Form Factor Substrate Dimensions
Table 5-3 Typical Assembly Equipment Limits
Table 6-1 Electrical Conductor Spacing
Table 6-2 Typical Relative Bulk Dielectric Constant of Printed Board Material
Table 6-3 Example Plane Sequences for a Six Layer Printed Board
Table 7-1 Effects of Material Type on Construction
Table 7-2 Emissivity Ratings for Certain Materials
Table 7-3 Printed Board Heatsink Assembly Preferences
Table 7-4 Comparative Reliability Matrix Component Lead/Termination Attachment
Table 9-1 Minimum Standard Fabrication Allowance for Interconnection Lands
Table 9-2 Annular Rings (Minimum)
Table 9-3 Minimum Drilled Hole Size for Buried Vias
Table 9-4 Minimum Drilled Hole Size for Blind Vias
Table 9-5 Minimum Hole Location Tolerance, dtp
Table 9-6 Through-Hole Diameters Minimum and Maximum and Aspect Ratio, mm [in]
Table 10-1 Internal Layer Foil Thickness After Processing
Table 10-2 External Conductor Thickness After Plating
Table 12-1 Appendix A Coupon Requirements
Table 12-2 Appendix B (Legacy) Coupon Requirements
Table A.1-1 IPC Coupons
Table A.2-1 AB/R Coupon Parameters, mm [in]
Table A.3-1 A/R Coupon Parameters, mm [in]
Table A.4-1 B/R Coupon Parameters, mm [in]
Table A.5-1 E Coupon Parameters, mm [in]
Table A.6-1 S Coupon Parameters, mm [in]
Table A.7-1 W Coupon Parameters, mm [in]
Table A.8-1 D Coupon Parameters, mm [in]
Table A.9-1 G Coupon Parameters, mm [in]
Table A.10-1 H Coupon Parameters, mm [in]
Table A.11-1 P Coupon Parameters, mm [in]
Table A.12-1 Z Coupon Parameters, mm [in]
Table B.1-1 IPC-2221 Legacy Coupons
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