Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications

✍ Scribed by Terry Stratoudakis

• Publisher: Artech House
• Year: 2021
• Tongue: English
• Leaves: 251
• Category: Library

✦ Synopsis

Real-time testing and simulation of open- and closed-loop radio frequency (RF) systems for signal generation, signal analysis and digital signal processing require deterministic, low-latency, high-throughput capabilities afforded by user reconfigurable field programmable gate arrays (FPGAs). This comprehensive book introduces LabVIEW FPGA, provides best practices for multi-FPGA solutions, and guidance for developing high-throughput, low-latency FPGA based RF systems. Written by a recognized expert with a wealth of real-world experience in the field, this is the first book written on the subject of FPGAs for radar and other RF applications.

✦ Table of Contents

Introduction to LabVIEW™ FPGA for RF, Radar, and Electronic
Warfare Applications
Preface
Acknowledgments
Chapter 1 Introduction.
1.1 What Is an FPGA?
1.2 History of FPGAs
1.2.1 Evolution of FPGA Tools
1.3 Selecting an FPGA
1.3.1 Build Your Own Board Approach
1.3.2 FPGA Platform Approach
1.3.3 Selecting FPGA Pros and Cons
1.4 Why LabVIEW FPGA?
1.4.1 LabVIEW FPGA Hardware
1.4.2 LabVIEW FPGA Math and Logic
1.4.3 LabVIEW FPGA Interfacing to the Host Computer
1.5 The Development Process
1.5.1 Risk Analysis
1.5.2 Estimates
1.5.3 Requirements Management
1.5.4 Source Code Control
1.5.5 Bug and Task Tracking
1.5.6 Document Management
1.5.7 Automated Builds
1.5.8 Technical Debt
1.5.9 Laboratory Information Management System
1.5.10 Development Process Conclusion
1.6 Book Overview
1.6.1 Chapter 2: How to Learn LabVIEW FPGA
1.6.2 Chapter 3: Background Technology
1.6.3 Chapter 4: LabVIEW FPGA
1.6.4 Chapter 5: LabVIEW FPGA RF Case Studies
1.6.5 Chapter 6: Looking Ahead
References
Chapter 2
How to Learn LabVIEW FPGA
2.1 Learning LabVIEW FPGA Versus VHDL/Verilog
2.2 Preconceived Notions
2.3 Four Stages of Competence
2.4 LabVIEW FPGA Learning Phases
2.4.1 Have a Problem to Solve
2.4.2 Software Model
2.4.3 Software Engineering
2.4.4 LabVIEW Proficiency
2.4.5 FPGA Knowledge
2.4.6 LabVIEW FPGA Learning Phases Conclusion
2.5 Users of LabVIEW FPGA
2.5.1 Existing LabVIEW Developer
2.5.2 Non-LabVIEW Software Developer
2.5.3 VHDL/Verilog Developer
2.5.4 Algorithm Expert
2.5.5 RF, Radar, and EW Subject Matter Expert
2.5.6 Management
2.6 Summary
References
Chapter 3
Background Technology
3.1 Introduction
3.2 History of FPGAs
3.2.1 Before FPGAs
3.2.2 Earlier FPGAs
3.2.3 Math/Digital Signal Processing Capability
3.2.4 The Specialization of FPGAs
3.3 Inside an FPGA
3.3.1 Electronics Kit Analogy
3.3.2 Logic Blocks
3.3.3 Interconnects
3.3.4 I/O
3.3.5 Clocks
3.3.6 Math on an FPGA
3.3.7 Memory on an FPGA
3.4 Benefits of FPGAs
3.4.1 Determinism
3.4.2 Low Latency
3.4.3 Parallelism
3.4.4 High Throughput
3.5 Industries and Applications
3.6 Compared to ASICs, CPUs, and GPUs
3.6.1 ASICs
3.6.2 CPUs
3.6.3 GPUs
3.7 Summary
References
Chapter 4
Using LabVIEW FPGA
4.1 Overview
4.2 A Systems Engineering Approach
4.2.1 Development Models
4.2.2 Requirements Gathering
4.2.3 Design
4.2.4 Minimum Viable Product
4.2.5 Risk Analysis
4.3 Generic LabVIEW FPGA Systems View
4.4 LabVIEW Environment
4.4.1 Setting Up LabVIEW
4.4.2 LabVIEW File Types
4.4.3 Example Finder
4.4.4 Context Help
4.4.5 Tools >> Options
4.4.6 LabVIEW Quick Drop
4.4.7 LabVIEW Bookmarks
4.4.8 Separate Source and Compiled LabVIEW Code
4.4.9 Reentrancy in LabVIEW VIs
4.4.10 What Is a subVI?
4.4.11 Polymorphic VIs
4.4.12 Object-Oriented Design in LabVIEW
4.5 Host Computer Functionalities and Interfacing
4.5.1 Host to or from the FPGA
4.5.2 To and From the VST
4.5.3 P2P Configurations
4.5.4 MGT Configurations
4.5.5 Disk Interfacing
4.5.6 Interfacing to Many FPGA Cards
4.5.7 Host Interfacing Conclusion
4.6 Inside the FPGA
4.6.1 To and From the FPGA
4.6.2 Inside the FPGA
4.7 Simulating the Design
4.7.1 Simulation Modes
4.7.2 Simulation Example
4.7.3 Simulation Summary
4.8  Compiling the FPGA VI
4.8.1 Compiling an FPGA
4.8.2 LabVIEW FPGA Compile Steps
4.8.3 Xilinx Compile Tools
4.8.4 Compile Locations
4.8.5 Compilation Hardware Considerations
4.8.6 Simultaneous Compiles
4.8.7 Multiple Compiles of the Same FPGA VI
4.8.8 Compile Failures
4.8.9 Periodic Compile Checks
4.8.10 Guidelines for Committing LabVIEW FPGA Compile Results
4.9 Debugging on Hardware
4.9.1 Streaming
4.9.2 Counters and Latches
4.9.3 Interactive Front Panel Communication
4.10 Export Options
4.10.1 Vivado Export
4.10.2 LabVIEW FPGA IP Export
4.11 Summary
References
Chapter 5
RF LabVIEW FPGA Case Studies
5.1 Overview
5.2 Problem Definition
5.3 NI Platform
5.3.1 Market Overview
5.4 Common NI FPGA Architectures
5.4.1 Summary
5.5 Components of an RF Test System
5.5.1 Front End
5.5.2 FPGA DSP
5.5.3 CPU/GPU DSP
5.5.4 Storage
5.6 Case Studies
5.6.1 NI VST
5.6.2 RTSA
5.6.3 Multichannel Phased Array Systems
5.6.4 Other Case Studies
References
Chapter 6
Looking Ahead
6.1 FPGA Overlays
6.1.1 NI VST as an FPGA Overlay
6.1.2 Xilinx PYNQ
6.2 SoC Architectures
6.3 FPGA Platforms
6.3.1 LabVIEW NXG
6.4 RISC-V
6.5 Echolocation in Nature
6.6 How to Stay Current
6.6.1 Publications and Online Resources
6.6.2 Recommended Conferences
6.7 Conclusions
References
Selected Bibliography
Selected Bibliography
National Instruments References
LabVIEW High Performance FPGA Developer’s Guide
CompactRIO Developer’s Guide
NI High-Speed Serial Instruments User Manual
NI-7931R, 7932R, and 7935R User Manual
Other LabVIEW FPGA Content on the NI’s Website
NI Center of Excellence
NI Training
Books
LabVIEW FPGA Books
LabVIEW Books
RF, EW, and Radar Books
FPGA Books
Management Books
Online Videos
Organizations and Periodicals
Online RF, Radar, and EW Resources
Vendor Resources
Summary
About the Author
Index