✦ LIBER ✦

Interleaving on Parallel DSP Architectures

✍ Scribed by Richter, Thomas ;Fettweis, Gerhard P.

No coin nor oath required. For personal study only.

📜 SIMILAR VOLUMES

Mapping interleaving laws to parallel tu

✍ Tarable, A.; Benedetto, S. 📂 Article 📅 2004 🏛 IEEE 🌐 English ⚖ 121 KB

Mapping interleaving laws to parallel tu

✍ Tarable, A.; Benedetto, S.; Montorsi, G. 📂 Article 📅 2004 🏛 IEEE 🌐 English ⚖ 218 KB

Parallel Processing Architecture for Sub

✍ Fazekas, K. 📂 Article 📅 2008 🏛 John Wiley and Sons 🌐 English ⚖ 666 KB

Variable-size interleaver design for par

✍ Dinoi, L.; Benedetto, S. 📂 Article 📅 2005 🏛 IEEE 🌐 English ⚖ 646 KB

Design of Prunable Interleavers for Para

✍ Tarable, A.; Dinoi, L.; Benedetto, S. 📂 Article 📅 2007 🏛 IEEE 🌐 English ⚖ 256 KB

A dynamically scheduled parallel DSP arc

✍ Guoning Liao; Guang R. Gao; Vinod K. Agarwal 📂 Article 📅 1994 🏛 Elsevier Science ⚖ 805 KB