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Interaction between Compilers and Computer Architectures

✍ Scribed by Sid-Ahmed-Ali Touati (auth.), Gyungho Lee, Pen-Chung Yew (eds.)


Publisher
Springer US
Year
2001
Tongue
English
Leaves
148
Series
The Springer International Series in Engineering and Computer Science 613
Edition
1
Category
Library

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✦ Synopsis


Effective compilers allow for a more efficient execution of application programs for a given computer architecture, while well-conceived architectural features can support more effective compiler optimization techniques. A well thought-out strategy of trade-offs between compilers and computer architectures is the key to the successful designing of highly efficient and effective computer systems. From embedded micro-controllers to large-scale multiprocessor systems, it is important to understand the interaction between compilers and computer architectures.
The goal of the Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT) is to promote new ideas and to present recent developments in compiler techniques and computer architectures that enhance each other's capabilities and performance. Interaction Between Compilers and Computer Architectures is an updated and revised volume consisting of seven papers originally presented at the Fifth Workshop on Interaction between Compilers and Computer Architectures (INTERACT-5), which was held in conjunction with the IEEE HPCA-7 in Monterrey, Mexico in 2001. This volume explores recent developments and ideas for better integration of the interaction between compilers and computer architectures in designing modern processors and computer systems.
Interaction Between Compilers and Computer Architectures is suitable as a secondary text for a graduate level course, and as a reference for researchers and practitioners in industry.

✦ Table of Contents


Front Matter....Pages i-xi
Equimax: A New Formulation of Optimal Register-Sensitive Scheduling for ILP Processors....Pages 1-19
An Efficient Semi-Hierarchical Array Layout....Pages 21-43
Impact of Tile-Size Selection for Skewed Tiling....Pages 45-68
Improving Software Pipelining by Hiding Memory Latency with Combined Loads and Prefetches....Pages 69-87
Register Allocation for Embedded System in the Presence of Java Exception....Pages 89-100
Is Compiling for Performance β€” Compiling for Power?....Pages 101-115
A Technology-Scalable Architecture for Fast Clocks and High ILP....Pages 117-139
Back Matter....Pages 141-143

✦ Subjects


Processor Architectures; Computer Systems Organization and Communication Networks; Computer Science, general; Software Engineering/Programming and Operating Systems; Programming Languages, Compilers, Interpreters


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