System Level Design (SLD) and Electronic System Level (ESL) Design are buzzwords of todayΠΡs Electronic Design Automation (EDA) industry. The idea is to raise the level of abstraction of design entry for future hardware systems beyond the register transfer level (RTL). This is necessitated by the increasing complexity of the systems, the immense gate count available on a single chip, the relatively slower growth in designer productivity, and decreasing design turn around time. Even though a number of languages and design environments have been proposed in the last few years which includes SystemC, Bluespec, SpecC, and System Verilog, none of these satisfy our wish list for a successful system level design language or framework. We want to model heterogeneous system-on-chips (SoCs) which can be based captured by a language capable of expressing and co-simulating multiple models of computation. We want to model behavior rather than structure, and want our SLD languages to support simulation of behavioral hierarchy, rather than structural ones available in the existing languages. We also want easier integration of frameworks and tools from various vendors and open source tools that not only supports design, verification, dynamic waveform viewing, coverage driven dynamic test generation within the same framework, we want to dynamically enable or disable some of the tools from the integrated framework to speed up simulation as needed. We also want open source Eclipse plug-in for SystemC or similar ESL languages. We want ability for dynamic reflection and introspection from a running simulation to provide us with information about simulation state and accordingly generate tests dynamically to fulfill coverage goals.Ingredients for Successful System Level Design Automation Methodologydiscusses these wish lists, provides detailed discussions on how our prototype implementations provide us with these much desired features.