Preface
Contents
Data-Centric Computing Paradigm Shift, and Domain-Specific Architecture and Hardware
1 Introduction
2 Data Centric, Computing Paradigm Shifts, Domain-Specific Designs
2.1 Latency
2.2 Security, and Privacy
2.3 Domain-Specific Architecture and Circuits
2.4 Low Quality Data
SRAM-Based In-Memory Computing: Circuits, Functions, and Applications
1 Introduction
2 Standard Memory Cell Design in SRAM
3 SRAM IMC/NMC Architectures and Designs
4 SRAM-IMC Based Search and Logic Operation
4.1 Search Operation
4.2 Boolean Logic AND, OR, NAND, NOR, XNOR, XOR, and IMC
5 Arithmetic Operations
5.1 Addition
5.2 Multiplication
5.3 SRAM Based Multiply-Accumulate Arithmetic Implementations
6 Potential Applications
6.1 CNNs Applications
6.2 Encryption Algorithms Application
6.3 Application for Machine Learning (ML) and Classification Algorithms
6.4 SRAM-IMC for CAM and Hamming Distance Computation
Proposed SRAM-IMC for Hamming Distance Computation
7 Challenges
7.1 Readout Precision vs. Signal Margin
7.2 Limitations of 6T SRAM
7.3 Process Variation
7.4 Read Disturb
7.5 Cell and Array Area
7.6 Multi-Bit Input Schemes for MAC Operations
8 Commercial Availability
In and Near-Memory Computing Using DRAM
1 Introduction
2 DRAM Organization
3 DRAM Access
4 DRAM Computing Architecture
4.1 Row Copy
4.2 Bulk Initialization
4.3 Bitwise Operation
5 Potential Applications
5.1 Accelerators for Machine Learning Using DRAM
5.2 IMC Using DRAM for Security Applications
True Random Number Generator (TRNG)
Physical Unclonable Function (PUF)
6 Challenges
7 Commercial Availability
MRAM-Based In-Memory Computing
1 Introduction
1.1 Chapter Organization
2 Overview
2.1 CMOS Integration
2.2 Basic Characteristics and Comparisons to Other Technologies
Speed
Power
Density
Data Retention and Endurance
3 Physics of Magnetic Tunnel Junctions
3.1 Critical Current Density
3.2 Dynamic Modeling
3.3 TMR
4 Chip Demonstrations and Commercialization
5 MRAM for In-Memory Computing
5.1 Possibilities and Challenges
5.2 Digital IMC
General-Purpose IMC
IMC for AI Applications
5.3 Analog IMC
STT-MRAM Crossbar Architectures
Neuromorphic MRAM-Based Systems
6 Case Study: A Mixed-Signal SNN Accelerator Using an STT Crossbar
6.1 2MTJ-2T Cell
6.2 Mapping SNN to the STT Crossbar
Noise Modeling
In-Memory Computing Using Phase Change Memory
1 Introduction
2 Operating Principle
2.1 Write Operation
2.2 Read Operation
2.3 Multi-Level Operation
3 Properties of PCM Devices
4 Potential Applications
4.1 Compressed Sensing and Recovery
4.2 Mixed-Precision IMC
4.3 Convolutional Neural Network (CNN) Inference
4.4 Spiking Neural Network (SNN) with PCM Synapses
4.5 Hyper-Dimensional Computing (HDC)
4.6 Similarity Search in Genomic Read Mapping
4.7 Case Study: PCM-Based IMC Array with Time-Domain Circuit for DNA Read Mapping
5 Challenges
6 Commercial Availability
Memristor-Based In-Memory Computing
1 Introduction
2 Operating Principles
2.1 Memristor Basics
2.2 Memristor Models
2.3 Memristor Crossbar
3 RRAM IMC Architecture and Designs
3.1 RRAM-Based Vector-Matrix Multiplication
3.2 RRAM-Based In-Memory Logic
3.3 RRAM-Based Neural Network Architectures
3.4 RRAM-Based Spiking Neural Network Architectures
3.5 RRAM-Based Hyperdimensional Computing
3.6 RRAM-Based Image Processing
3.7 RRAM-Based Image Compression
3.8 RRAM-Based Image Enhancement
4 Challenges
4.1 Device Level
Conductance Tuning Scheme
State Disturbance
Resistance Ratio
Symmetry of the Device
Crossbar Nanowire Resistance
4.2 Peripheral Circuit Level
Sneak Path Currents
Write/Access Latency
Optimizing Peripheral Circuitry
RESET Operation Before Every Write
4.3 System Level
Map Matrix Values to Memristor Conductance
Negative Value Representation Using Memristor Conductance
Mapping Algorithms and Hardware Training Schemes
5 Case Study: Transformer Attention Acceleration on Memristor
5.1 Performance Assessment and Discussion
6 Commercial Availability
In-Memory Computing Using FLASH Memory
1 Potential Applications
2 Challenges
3 Commercial Availability
Reference
Index