Impact of the memory interface structure in the memory-processor integrated architecture for computer vision

✍ Scribed by Youngsik Kim; Tack-Don Han; Shin-Dug Kim

• Publisher: Elsevier Science
• Year: 2000
• Tongue: English
• Weight: 744 KB
• Volume: 46
• Category: Article
• ISSN: 1383-7621
• DOI: 10.1016/s1383-7621(99)00005-3

✦ Synopsis

The memory-based processor array (MPA) was previously designed as an eective memory-processor integrated architecture. The MPA can be easily attached into any host system via memory interface. In this paper, the impact of the memory interface structure is analytically analyzed for computer vision tasks. An analytical model is constructed to describe the characteristics of the memory interface structure. Performance improvement for the memory interface model of the MPA system can be 6±40% for vision tasks consisting of sequential and data parallel tasks. Mapping algorithms to implement convolution and connected component labeling on the MPA are also presented. The asymptotic time complexities of the algorithms are evaluated to verify the cost-eectiveness and the eciency of the MPA system.