✦ LIBER ✦

[IEEE its Applications (CSPA) - Penang, Malaysia (2011.03.4-2011.03.6)] 2011 IEEE 7th International Colloquium on Signal Processing and its Applications - Logical circuit gate sizing using MPSO guided by Logical Effort - An examination of the 8-stage full adder circuit

✍ Scribed by Johari, A.; Mohamed, S.; Halim, A. K.; Yassin, I. M.; Hassan, H. A.

No coin nor oath required. For personal study only.

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