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[IEEE ESSCIRC 2011 - 37th European Solid State Circuits Conference - Helsinki, Finland (2011.09.12-2011.09.16)] 2011 Proceedings of the ESSCIRC (ESSCIRC) - A 40nm 50S/s–8MS/s ultra low voltage SAR ADC with timing optimized asynchronous clock generator

✍ Scribed by Sekimoto, Ryota; Shikata, Akira; Kuroda, Tadahiro; Ishikuro, Hiroki

No coin nor oath required. For personal study only.

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