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[IEEE Comput. Soc Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) - Eilat, Israel (2-6 April 2000)] Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586) - Automated synthesis of micro-pipelines from behavioral Verilog HDL

✍ Scribed by Blunno, I.; Lavagno, L.

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✍ Ligthart, M.; Fant, K.; Smith, R.; Taubin, A.; Kondratyev, A. 📂 Article 📅 2000 🏛 IEEE Comput. Soc 🌐 English ⚖ 122 KB