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[IEEE Comput. Soc Parelec 2000 Internaitonal Symposium on Parallel Computing in Electrical Engineering - Trois-Rivieres, Que., Canada (27-30 Aug. 2000)] Proceedings International Conference on Parallel Computing in Electrical Engineering. PARELEC 2000 - A VLSI systolic array architecture for computation of third-order cumulants for two-dimensional signals

✍ Scribed by Musallam, Z.H.; Ahmed, R.E.; Alshebeili, S.A.

Book ID: 126731451
Publisher: IEEE Comput. Soc
Year: 2000
Weight: 372 KB
Category: Article
ISBN-13: 9780769507590
DOI: 10.1109/PCEE.2000.873616

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