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[IEEE Comput. Soc International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN 2000 - Dallas, TX, USA (7-9 Dec. 2000)] Proceedings International Symposium on Parallel Architectures, Algorithms and Networks. I-SPAN 2000 - Pipelining router design improves parallel system performance

✍ Scribed by Carrion, C.; Gregorio, A.; Beivideo, R.

Book ID: 126690586
Publisher: IEEE Comput. Soc
Year: 2000
Weight: 558 KB
Category: Article
ISBN-13: 9780769509365
DOI: 10.1109/ISPAN.2000.900285

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