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[IEEE BMAS 2005. 2005 IEEE International Behavioral Modeling and Simulation Workshop, 2005. - San Jose, CA, USA (Sept. 22-23, 2005)] BMAS 2005. Proceedings of the 2005 IEEE International Behavioral Modeling and Simulation Workshop, 2005. - A multiple-rotating-clock-phase architecture for digital data recovery circuits using verilog-A

✍ Scribed by Ahmed, S.I.; Kwasniewski, T.A.

Book ID: 126618644
Publisher: IEEE
Year: 2005
Weight: 702 KB
Category: Article
ISBN-13: 9780780393523
DOI: 10.1109/BMAS.2005.1518197

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