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[IEEE ASP-DAC '97: Asia and South Pacific Design Automation Conference - Chiba, Japan (28-31 Jan. 1997)] Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference - RTL verification of timed asynchronous and heterogeneous systems using symbolic model checking

✍ Scribed by Vakilotojar, V.; Beerel, P.A.

Book ID: 126639608
Publisher: IEEE
Year: 1997
Weight: 964 KB
Category: Article
ISBN-13: 9780780336629
DOI: 10.1109/ASPDAC.1997.600112

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