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[IEEE ASP-DAC 2005. Asia and South Pacific Design Automation Conference 2005 - Shanghai, China (18-21 Jan. 2005)] Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. - Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling

✍ Scribed by Jeng-Liang Tsai, ; Chung-Ping Chen, C.

Book ID: 126705183
Publisher: IEEE
Year: 2005
Weight: 675 KB
Volume: 2
Category: Article
ISBN-13: 9780780387362
DOI: 10.1109/ASPDAC.2005.1466549

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