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[IEEE 5th IEEE Conference on Nanotechnology, 2005. - Nagoya, Japan (July 11-15, 2005)] 5th IEEE Conference on Nanotechnology, 2005. - Buffer design trade-offs for single electron logic gates

✍ Scribed by Lageweg, C.; Cotofana, S.; Vassiliadis, S.

No coin nor oath required. For personal study only.

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