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[IEEE 43rd IEEE Midwest Symposium on Circuits and Systems - Lansing, MI, USA (8-11 Aug. 2000)] Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) - A negative conductance voltage gain enhancement technique for low voltage high speed CMOS op amp design

✍ Scribed by Jie Yan, ; Geiger, R.L.

Book ID: 115546843
Publisher: IEEE
Year: 2000
Tongue: English
Weight: 297 KB
Volume: 1
Category: Article
ISBN-13: 9780780364752
DOI: 10.1109/mwscas.2000.951693

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