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[IEEE 21st International Conference on VLSI Design (VLSID 2008) - Hyderabad, India (2008.01.4-2008.01.8)] 21st International Conference on VLSI Design (VLSID 2008) - A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits

✍ Scribed by Sambamurthy, Sriram; Abraham, Jacob A.; Tupuri, Raghuram S.

No coin nor oath required. For personal study only.

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