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[IEEE 2013 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC) - Enathi, Tamilnadu, India (2013.12.26-2013.12.28)] 2013 IEEE International Conference on Computational Intelligence and Computing Research - VLSI implementation of reduced complexity wallace multiplier using energy efficient CMOS full adder

✍ Scribed by Khan, Shahebaj; Kakde, Sandeep; Suryawanshi, Yogesh

Book ID: 125542966
Publisher: IEEE
Year: 2013
Weight: 661 KB
Category: Article
ISBN: 1479915955
DOI: 10.1109/ICCIC.2013.6724141

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