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[IEEE 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) - Karlsruhe, Germany (2013.09.9-2013.09.11)] 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) - Formal system-on-chip verification: An operation-based methodology and its perspectives in low power design

โœ Scribed by Urdahl, Joakim; Udupi, Shrinidhi; Stoffel, Dominik; Kunz, Wolfgang

Book ID
126250758
Publisher
IEEE
Year
2013
Weight
261 KB
Category
Article
ISBN
1479911704

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[IEEE 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) - Karlsruhe, Germany (2013.09.9-2013.09.11)] 2013 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) - Design of variable latency adder based on present and transitional states prediction
โœ Yang, Xinghua; Qiao, Fei; Liu, Chang; Yang, Huazhong ๐Ÿ“‚ Article ๐Ÿ“… 2013 ๐Ÿ› IEEE โš– 445 KB