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[IEEE 2013 18th International Conference on Digital Signal Processing (DSP) - Fira (2013.4.27-2013.4.30)] 2013 Saudi International Electronics, Communications and Photonics Conference - Synthesizable System Verilog model for hardware metastability in formal verification

✍ Scribed by Ismail, Ahmed; Saafan, Haytham

Book ID: 121648532
Publisher: IEEE
Year: 2013
Weight: 354 KB
Category: Article
ISBN: 1467361941
DOI: 10.1109/SIECPC.2013.6550996

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