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[IEEE 2012 VIII Southern Conference on Programmable Logic (SPL) - Bento Goncalves (2012.03.20-2012.03.23)] 2012 VIII Southern Conference on Programmable Logic - FPGA implementation of the parity check node for min-sum LDPC decoders

✍ Scribed by Gutierrez, F.; Corral-Briones, G.; Morero, D.; Goette, T.; Ramos, F.

Book ID: 126826805
Publisher: IEEE
Year: 2012
Weight: 315 KB
Category: Article
ISBN: 146730185X
DOI: 10.1109/spl.2012.6211802

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