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[IEEE 2012 IEEE Symposium on VLSI Circuits - Honolulu, HI, USA (2012.06.13-2012.06.15)] 2012 Symposium on VLSI Circuits (VLSIC) - A clock jitter reduction circuit using gated phase blending between self-delayed clock edges

✍ Scribed by Niitsu, Kiichi; Harigai, Naohiro; Hirabayashi, Daiki; Oki, Daiki; Sakurai, Masato; Kobayashi, Osamu; Yamaguchi, Takahiro J.; Kobayashi, Haruo

Book ID: 125815919
Publisher: IEEE
Year: 2012
Weight: 342 KB
Category: Article
ISBN: 1467308455
DOI: 10.1109/VLSIC.2012.6243830

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