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[IEEE 2012 IEEE Symposium on VLSI Circuits - Honolulu, HI, USA (2012.06.13-2012.06.15)] 2012 Symposium on VLSI Circuits (VLSIC) - An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration

✍ Scribed by Lee, Seung-Chul; Elies, Brian; Chiu, Yun

No coin nor oath required. For personal study only.

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